Patents by Inventor Daniele Vimercati

Daniele Vimercati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Access schemes for section-based data protection in a memory device
    Patent number: 10431281
    Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Jahanshir Javanifard
  • SELF-REFERENCE FOR FERROELECTRIC MEMORY
    Publication number: 20190287600
    Abstract: Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.
    Type: Application
    Filed: March 27, 2019
    Publication date: September 19, 2019
    Inventor: Daniele Vimercati
  • CURRENT SEPARATION FOR MEMORY SENSING
    Publication number: 20190287601
    Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventor: Daniele Vimercati
  • Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines
    Patent number: 10410709
    Abstract: Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Duane R. Mills
  • Self-referencing sensing schemes with coupling capacitance
    Patent number: 10395697
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Charge mirror-based sensing for ferroelectric memory
    Patent number: 10395718
    Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Xinwei Guo, Daniele Vimercati
  • Differential amplifier schemes for sensing memory cells
    Patent number: 10388361
    Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Stefan Frederik Schippers, Xinwei Guo
  • Wear leveling for random access and ferroelectric memory
    Patent number: 10388351
    Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills
  • SELF-REFERENCING SENSING SCHEMES WITH COUPLING CAPACITANCE
    Publication number: 20190244641
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • CURRENT SEPARATION FOR MEMORY SENSING
    Publication number: 20190189178
    Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventor: Daniele Vimercati
  • OFFSET CANCELLATION FOR LATCHING IN A MEMORY DEVICE
    Publication number: 20190147933
    Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Inventor: Daniele Vimercati
  • Self-reference for ferroelectric memory
    Patent number: 10290341
    Abstract: Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • GROUND REFERENCE SCHEME FOR A MEMORY CELL
    Publication number: 20190130955
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 2, 2019
    Inventors: Daniele Vimercati, Scott James Derner, Umberto Di Vincenzo, Christopher Johnson Kawamura, Eric S. Carman
  • DUAL MODE FERROELECTRIC MEMORY CELL OPERATION
    Publication number: 20190122717
    Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.
    Type: Application
    Filed: November 8, 2018
    Publication date: April 25, 2019
    Inventor: Daniele Vimercati
  • DUAL MODE FERROELECTRIC MEMORY CELL OPERATION
    Publication number: 20190122718
    Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.
    Type: Application
    Filed: November 8, 2018
    Publication date: April 25, 2019
    Inventor: Daniele Vimercati
  • CHARGE MIRROR-BASED SENSING FOR FERROELECTRIC MEMORY
    Publication number: 20190108867
    Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
    Type: Application
    Filed: November 13, 2018
    Publication date: April 11, 2019
    Inventors: Xinwei Guo, Daniele Vimercati
  • Interrupted write operation in a serial interface memory with a portion of a memory address
    Patent number: 10248592
    Abstract: Subject matter disclosed herein relates to read and write processes of a memory device.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 2, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Graziano Mirichigni, Daniele Vimercati
  • CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL
    Publication number: 20190096466
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
    Type: Application
    Filed: November 27, 2018
    Publication date: March 28, 2019
    Inventor: Daniele Vimercati
  • CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL
    Publication number: 20190096467
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
    Type: Application
    Filed: November 27, 2018
    Publication date: March 28, 2019
    Inventor: Daniele Vimercati
  • WEAR LEVELING FOR RANDOM ACCESS AND FERROELECTRIC MEMORY
    Publication number: 20190066752
    Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills