Patents by Inventor Daniele Vimercati

Daniele Vimercati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7902882
    Abstract: Embodiments include but are not limited to apparatuses and systems including an output buffer including an input terminal for receiving an input signal, an output terminal for outputting an output signal, and a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: March 8, 2011
    Inventors: Daniele Vimercati, Riccardo Muzzetto
  • Publication number: 20100164558
    Abstract: Embodiments include but are not limited to apparatuses and systems including an output buffer including an input terminal for receiving an input signal, an output terminal for outputting an output signal, and a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Inventors: Daniele Vimercati, Riccardo Muzzetto
  • Publication number: 20100165724
    Abstract: Embodiments include but are not limited to apparatuses and systems including a plurality of memory cells, each memory cell including a selector and a storage element coupled to the selector. A word-line may be coupled to the memory cells and may have a word-line driver including a pull-up resistor coupled to the selectors for the memory cells to access respective storage elements of the memory cells. Other embodiments may be described and claimed.
    Type: Application
    Filed: November 19, 2009
    Publication date: July 1, 2010
    Inventors: Fabio Pellizzer, Agostino Pirovano, Andrea Redaelli, Daniele Vimercati
  • Patent number: 7646644
    Abstract: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: January 12, 2010
    Inventors: Efrem Bolandrina, Daniele Vimercati, Corrado Villa
  • Patent number: 7567107
    Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: July 28, 2009
    Inventors: Daniele Vimercati, Stefan Schippers, Corrado Villa, Yuri Zambelli
  • Patent number: 7554861
    Abstract: A memory device is proposed.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: June 30, 2009
    Inventors: Daniele Vimercati, Efrem Bolandrina
  • Patent number: 7532060
    Abstract: In a charge-pump device, a charge-pump circuit has an input, which is connected to a supply line and receives a supply voltage, and an output; in the charge-pump circuit a first elementary stage defines a first transfer node and a second transfer node that can be connected respectively to the input and to the output, and has at least one first phase input. In addition, in the first elementary stage a first switching element is arranged between the first transfer node and the second transfer node, has a control terminal receiving a control signal, and is closed during a charge-transfer interval; and first charge-storage means are connected between the control terminal and the first phase input. In the first elementary stage, a voltage-booster stage has an input connected to the first phase input of the first elementary stage, and an output connected to the first charge-storage means and supplies a boosted phase signal; in particular, the voltage-booster stage is operative during the charge-transfer interval.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: May 12, 2009
    Inventors: Carmela Albano, Daniele Vimercati
  • Patent number: 7521989
    Abstract: A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: April 21, 2009
    Inventors: Daniele Vimercati, Osama Khouri, Sara Fiorina
  • Patent number: 7515464
    Abstract: A method is for reducing possible errors in execution of simultaneous read and verify operations of data being modified in first and second different partitions of a memory device caused by turning on or off of a first partition's bank of sense amplifiers while a critical discrimination phase is being carried out by the second partition's bank of sense amplifiers. The method may include establishing an augmented duration of one of the read and verify operations exceeding a duration of the first partition's critical discrimination phase. The method may conditionally delay generation of a turn on or turn off signal of the first partition by a time determined by a command of termination, or by a beginning of the critical discrimination phase of the second partition when the other of the read and verify operations is in progress.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: April 7, 2009
    Inventors: Daniele Vimercati, Andrea Martinelli, Efrem Bolandrina
  • Patent number: 7345905
    Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: March 18, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Pio, Efrem Bolandrina, Daniele Vimercati
  • Patent number: 7321512
    Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: January 22, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Vimercati, Marco Onorato, Carmela Albano, Mounia El-Moutaouakil
  • Publication number: 20070279980
    Abstract: The invention relates to a reading method of a non-volatile electronic device of the multilevel type, the device comprises at least one first and one second memory bank each of said memory banks comprises a plurality of transistor cells organized in a matrix with a plurality of rows or wordlines and a plurality of columns or bitlines, at least one of said transistor cells being a reference cell containing a reference value, said bitlines being connected to at least one group of sense amplifiers, which comprises in turn a reference terminal and at least one signal output. A crossed electric connection is provided between the reference terminal of at least one group of sense amplifiers of the first memory bank to an output of a subgroup of sense amplifiers of the second memory bank, and vice versa, and the subgroup of sense amplifiers associated with a memory bank is used as a connection to said reference cell during the reading step of the other memory bank.
    Type: Application
    Filed: May 24, 2007
    Publication date: December 6, 2007
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Stefan Schippers, Daniele Vimercati, Efrem Bolandrina
  • Publication number: 20070223168
    Abstract: Local suppression of a disturbance of a reference line is accomplished by supplying, on an internal node, a Band Gap voltage signal that is stable in temperature and power supply; driving a controlled current generator generating a controlled current signal by means of the Band Gap voltage signal; locally suppressing a disturbance of the reference line by means of a disturbance suppression circuit connected to the internal node acting on the Band Gap voltage signal; and mirroring a current signal generated on the reference line which is an output terminal of the Band Gap circuitry.
    Type: Application
    Filed: February 27, 2007
    Publication date: September 27, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele Vimercati, Efrem Bolandrina, Pierguido Garofalo
  • Publication number: 20070217257
    Abstract: A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the bank of sense amplifiers of the other partition. The method includes establishing an increase in duration of one of the two operations for exceeding a minimum duration of a critical discrimination phase for the banks of sense amplifiers, and conditionally delaying conditioning of generation of a turn on or turn off signal of the bank of sense amplifiers for the partition in which the operation of an increase in duration is in progress by a predetermined time. The predetermined time is based on a command of termination, or a beginning of the critical discrimination phase by the bank of sense amplifiers of the other partition wherein the other operation is in progress.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 20, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele Vimercati, Andrea Martinelli, Efrem Bolandrina
  • Publication number: 20070216449
    Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 20, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele Vimercati, Stefan Schippers, Corrado Villa, Yuri Zambelli
  • Patent number: 7272059
    Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: September 18, 2007
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Daniele Vimercati, Sara Fiorina, Efrem Bolandrina, Stefan Schippers, Marco Onorato
  • Publication number: 20070133666
    Abstract: A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.
    Type: Application
    Filed: November 16, 2006
    Publication date: June 14, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele Vimercati, Claudio Nava, Christophe Laurent
  • Publication number: 20070036014
    Abstract: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 15, 2007
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Efrem Bolandrina, Daniele Vimercati, Corrado Villa
  • Publication number: 20060250852
    Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective volage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.
    Type: Application
    Filed: May 3, 2006
    Publication date: November 9, 2006
    Applicant: STMicroelectronics S.r.I
    Inventors: Daniele Vimercati, Marco Onorato, Carmela Albano, Mounia El-Moutaouakil
  • Publication number: 20060215463
    Abstract: A memory device is proposed.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 28, 2006
    Inventors: Daniele Vimercati, Efrem Bolandrina