Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract: In a charge-pump device, a charge-pump circuit has an input, which is connected to a supply line and receives a supply voltage, and an output; in the charge-pump circuit a first elementary stage defines a first transfer node and a second transfer node that can be connected respectively to the input and to the output, and has at least one first phase input. In addition, in the first elementary stage a first switching element is arranged between the first transfer node and the second transfer node, has a control terminal receiving a control signal, and is closed during a charge-transfer interval; and first charge-storage means are connected between the control terminal and the first phase input. In the first elementary stage, a voltage-booster stage has an input connected to the first phase input of the first elementary stage, and an output connected to the first charge-storage means and supplies a boosted phase signal; in particular, the voltage-booster stage is operative during the charge-transfer interval.

Abstract: A reading method for a nonvolatile memory device, wherein the gate terminals of the array memory cell and of the reference memory cell are supplied with a same reading voltage having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell are determined on the basis of the modification order of the current-conduction states of the array memory cell and of the reference memory cell.

Abstract: A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.

Abstract: A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract: A reading method for a nonvolatile memory device, wherein the gate terminals of the array memory cell and of the reference memory cell are supplied with a same reading voltage having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell are determined on the basis of the modification order of the current-conduction states of the array memory cell and of the reference memory cell.