Patents by Inventor Danny Clavette

Danny Clavette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10656217
    Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Aliaksandr Subotski, Giuseppe Bernacchia, Danny Clavette, Benjamim Tang
  • Publication number: 20190267362
    Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: Thomas Feil, Danny Clavette, Paul Ganitzer, Martin Poelzl, Carsten von Koblinski
  • Publication number: 20190267343
    Abstract: In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: Thomas Feil, Danny Clavette, Carsten von Koblinski
  • Patent number: 10298123
    Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Danny Clavette, Kang Peng, Keng Chen, Mark A. Crowther
  • Publication number: 20190137575
    Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Aliaksandr Subotski, Giuseppe Bernacchia, Danny Clavette, Benjamim Tang
  • Publication number: 20190124773
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Publication number: 20190103811
    Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Inventors: Danny Clavette, Kang Peng, Keng Chen, Mark A. Crowther
  • Patent number: 10206286
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10197636
    Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Aliaksandr Subotski, Giuseppe Bernacchia, Danny Clavette, Benjamim Tang
  • Publication number: 20190018071
    Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Inventors: Aliaksandr Subotski, Giuseppe Bernacchia, Danny Clavette, Benjamim Tang
  • Publication number: 20180376598
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10153697
    Abstract: A multi-phase power supply circuit includes multiple phases to convert an input voltage into a respective output voltage to power a load. A first phase of the multi-phase power supply includes a core power supply circuit including, for example, high side switch circuitry and low side switch circuitry. During normal operation, the core power supply circuit converts an input voltage into a respective output voltage to power a load. To provide failure mode protection with respect to the core power supply circuit and prevent a failure mode in which the first phase would otherwise produce a dangerous over-voltage condition, the first power supply phase includes an input voltage switch circuit disposed between an input voltage source and the core power supply circuit. The input voltage switch circuit provides a way of preventing the input voltage from being conveyed to the core power supply circuit during a failure mode.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Mudassar Khatib, Danny Clavette
  • Publication number: 20180351452
    Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Inventors: Danny Clavette, Kang Peng, Keng Chen, Mark A. Crowther
  • Patent number: 10135335
    Abstract: In some examples, a device comprises an inductor and a package comprising at least one power device. The package is attached to the inductor by an adhesion layer, and the inductor comprises one or more leads. A first lead of the one or more leads is configured to conduct electricity between the at least one power device and the inductor, and a surface of the first lead and a surface of the package are substantially co-planar.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 10122256
    Abstract: A switched-capacitor converter includes a plurality of legs coupled between the input and a rectifier at the output. Each leg includes a capacitor. A first group of legs is coupled to a first branch of the rectifier, and a second group is coupled to a second branch of the rectifier. A switch device is connected to each leg. The controller alternates switching of the switch devices connected to the first and second groups of legs to transfer energy from input to output. The switching is modified based on zero-crossing information which indicates when current through each switch device crosses or nearly crosses zero, so that each switch device connected to the same group of legs is turned off when current through that switch device crosses or nearly crosses zero and remains off until all switch devices connected to that group have been turned off for a predetermined amount of time.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Amir Babazadeh, Rakesh Renganathan, Danny Clavette, Christian Rainer
  • Patent number: 10119999
    Abstract: An example system comprises first circuitry (such as a first integrated circuit device having a limited number of input/output pins) and second circuitry (such as a second integrated circuit device having a limited number of input output pins). The second circuitry is communicatively coupled to receive communications over a communication link from the first circuitry. In one embodiment, the first circuitry includes a monitor circuit. The monitor circuit monitors a voltage rail inputted to power the first circuitry. The monitor circuit initiates switching between transmitting a control signal (such as status information indicating whether the first circuitry is powered correctly) and a data signal over a communication link from the first circuitry to second circuitry depending upon the magnitude of the voltage rail. For example, when the first circuit is properly powered, the monitor circuit initiates transmission of the data signal over the communication link to the second circuitry.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Prasan Kasturi, Rakesh Renganathan, Danny Clavette, Rong Guo
  • Publication number: 20180294719
    Abstract: A multi-phase power supply circuit includes multiple phases to convert an input voltage into a respective output voltage to power a load. A first phase of the multi-phase power supply includes a core power supply circuit including, for example, high side switch circuitry and low side switch circuitry. During normal operation, the core power supply circuit converts an input voltage into a respective output voltage to power a load. To provide failure mode protection with respect to the core power supply circuit and prevent a failure mode in which the first phase would otherwise produce a dangerous over-voltage condition, the first power supply phase includes an input voltage switch circuit disposed between an input voltage source and the core power supply circuit. The input voltage switch circuit provides a way of preventing the input voltage from being conveyed to the core power supply circuit during a failure mode.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Mudassar Khatib, Danny Clavette
  • Publication number: 20180233453
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 9966341
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 8, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette