Patents by Inventor Danny Clavette

Danny Clavette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013276
    Abstract: According to one configuration, an inductor device comprises core material and at least a first electrically conductive path. The core material is fabricated from magnetically permeable material. The first electrically conductive path extends axially through the core material from a proximal end of the inductor device to a distal end of the inductor device. The core material is operable to confine first magnetic flux generated from first current flowing through the first electrically conductive path. The inductor device further includes a gap in the core material. The gap (gas or solid material) has a different magnetic permeability than the core material. Inclusion of the gap in the core material provides a way to tune an inductance of the inductor device and increase a magnetic saturation level of the inductor device. The core material includes any number of electrically conductive paths and corresponding gaps.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventors: Danny Clavette, Gerald Deboy, Roberto RIZZOLATTI, Otto WIEDENBAUER, Yong Zhou
  • Publication number: 20220007512
    Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; an electrical interface for a processor substrate at the first main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage. The power device module has at least one contact configured to receive the voltage provided at the second main side of the electrically insulating material. Distribution circuitry embedded in the electrically insulating material is configured to carry the lower voltage provided by the power device module to the first main side of the electrically insulating material.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Inventors: Danny Clavette, Darryl Galipeau
  • Patent number: 11183934
    Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 23, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Danny Clavette
  • Publication number: 20210335739
    Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 28, 2021
    Inventors: Thomas Feil, Danny Clavette, Paul Ganitzer, Martin Poelzl, Carsten von Koblinski
  • Publication number: 20210321519
    Abstract: A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventor: Danny Clavette
  • Patent number: 11147165
    Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor substrate at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage at the first main side of the electrically insulating material.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Danny Clavette, Darryl Galipeau
  • Patent number: 11121708
    Abstract: A power module includes: an embedding structure comprising an electrically insulating body; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a terminal of the embedding structure through one or more second electrically conductive paths embedded in the electrically insulating body.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Danny Clavette, Bang Sup Lee
  • Patent number: 11101221
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Publication number: 20210242863
    Abstract: A power module includes: an embedding structure comprising an electrically insulating body; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a terminal of the embedding structure through one or more second electrically conductive paths embedded in the electrically insulating body.
    Type: Application
    Filed: January 4, 2021
    Publication date: August 5, 2021
    Inventors: Danny Clavette, Bang Sup Lee
  • Patent number: 11081457
    Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Danny Clavette, Paul Ganitzer, Martin Poelzl, Carsten von Koblinski
  • Patent number: 11075577
    Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 27, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Danny Clavette, Kang Peng, Keng Chen, Mark A. Crowther
  • Publication number: 20210225745
    Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Robert Fehler, Eung San Cho, Danny Clavette, Petteri Palm
  • Patent number: 11069639
    Abstract: In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Danny Clavette, Carsten von Koblinski
  • Patent number: 11071206
    Abstract: A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is within an operating range of the processor and below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Danny Clavette
  • Publication number: 20210218334
    Abstract: A method of controlling a power converter includes: generating a modulation signal for controlling a phase current of a power stage of the power converter such that an output voltage of the power converter follows a load line having a slope that determines a rate of change of the output voltage as a function of load current; receiving a signal which indicates a target voltage regulation setpoint; and overriding the load line when the signal is active, such that the output voltage follows the target voltage regulation setpoint instead of the load line when the signal is present at the interface.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: Jayadevan Radhakrishnan, Danny Clavette
  • Publication number: 20210120675
    Abstract: A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is within an operating range of the processor and below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventor: Danny Clavette
  • Publication number: 20210119542
    Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventor: Danny Clavette
  • Publication number: 20210120676
    Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor substrate at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage at the first main side of the electrically insulating material.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventors: Danny Clavette, Darryl Galipeau
  • Patent number: 10917082
    Abstract: A power module includes: an embedding structure comprising an electrically insulating body, first terminals at a first side of the electrically insulating body, and second terminals at a second side of the electrically insulating body opposite the first side; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip contacting the first set of terminals at the first side of the electrically insulating body and comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a corresponding one of the second terminals through one or more second electrically conductive paths embedded in the electrically insulating body.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Danny Clavette, Bang Sup Lee
  • Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau