Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.

Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.

Abstract: In some examples, a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment. The device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment. The device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor. The device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.

Abstract: In some examples, a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment. The device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment. The device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor. The device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.

Abstract: In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.

Abstract: In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.

Abstract: In some examples, a device comprises an inductor and a package comprising at least one power device. The package is attached to the inductor by an adhesion layer, and the inductor comprises one or more leads. A first lead of the one or more leads is configured to conduct electricity between the at least one power device and the inductor, and a surface of the first lead and a surface of the package are substantially co-planar.

Abstract: In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

Abstract: A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

Abstract: In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

Abstract: An example system comprises first circuitry (such as a first integrated circuit device having a limited number of input/output pins) and second circuitry (such as a second integrated circuit device having a limited number of input output pins). The second circuitry is communicatively coupled to receive communications over a communication link from the first circuitry. In one embodiment, the first circuitry includes a monitor circuit. The monitor circuit monitors a voltage rail inputted to power the first circuitry. The monitor circuit initiates switching between transmitting a control signal (such as status information indicating whether the first circuitry is powered correctly) and a data signal over a communication link from the first circuitry to second circuitry depending upon the magnitude of the voltage rail. For example, when the first circuit is properly powered, the monitor circuit initiates transmission of the data signal over the communication link to the second circuitry.

Abstract: A driver circuitry includes a capacitor, a first switch, and a second switch. The capacitor includes a first node and a second node. The first switch is electrically coupled to the first node of the capacitor. The second switch is electrically coupled to the second node of the capacitor. Additionally, the second node of the capacitor and the second switch are electrically coupled to an output pin of the driver circuitry operable to drive an external switch. As discussed herein, settings of the first switch and the second switch control a voltage outputted from the output pin and charging of the capacitor.

Abstract: A driver circuitry includes a capacitor, a first switch, and a second switch. The capacitor includes a first node and a second node. The first switch is electrically coupled to the first node of the capacitor. The second switch is electrically coupled to the second node of the capacitor. Additionally, the second node of the capacitor and the second switch are electrically coupled to an output pin of the driver circuitry operable to drive an external switch. As discussed herein, settings of the first switch and the second switch control a voltage outputted from the output pin and charging of the capacitor.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A headroom compensation circuit for a voltage converter for ensuring that there is adequate headroom voltage to enable accurate operation of the current sense amplifier sensing the output current of the converter, the headroom compensation circuit comprising an error amplifier for comparing an output voltage of the converter to a reference voltage to set the converter output voltage; and a circuit for providing a bias current to an input of the error amplifier when a supply voltage to the current sense amplifier within a predefined threshold of the converter output voltage to cause the error amplifier to reduce the converter output voltage thereby to increase the headroom voltage for the current sense amplifier, said headroom voltage being defined as a voltage between the supply voltage to the current sense amplifier and said converter output voltage.

Abstract: A circuit for calibrating an oscillating ramp signal to a variable DC reference signal comprising a circuit for setting a predetermined time period during which a charging capacitor can charge and thus determining a ramp oscillator frequency; a variable current source for providing a charging current to the charging capacitor; a circuit for selecting the charging current fed by the variable current source to said charging capacitor; and a circuit for comparing the oscillating ramp signal to the variable DC reference signal and for supplying a signal to the selecting circuit for controlling the amount of current supplied to said charging capacitor thereby determining the charging voltage across said capacitor at the end of said predetermined time period.