Abstract: In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack; and removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures.

Abstract: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.

Abstract: One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.

Abstract: A method of forming a floating gate structure is disclosed, and includes modifying the etch chemistry of a plasma treated reactive ion etch process using an inert atom to physically damage a dielectric region. The damaged dielectric region is subsequently etched using a wet etch process.

Abstract: An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: A method of operating a memory array includes providing an array of memory cells arranged in rows and columns. Each column comprises a NAND unit cell including a plurality of memory cells coupled together serially. The plurality of memory cells of each NAND unit cell share a common well. The common well of each column is separated from common wells of adjacent columns by an isolation region. Each NAND unit cell includes a select gate transistor coupled to a memory cell in the column. A source of the select gate transistor is coupled to the common well of the NAND unit cell. The method includes accessing a first memory cell in a column by biasing the common well of the NAND unit cell of the first memory cell differently than the common well of other NAND unit cells are biased.

Abstract: In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.

Abstract: A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.

Abstract: The invention relates to a method for producing a PCM memory element and to a corresponding PCM element.

Abstract: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

Abstract: A method for fabricating a sublithographic contact structure in a memory cell in a semiconductor component is disclosed. In one embodiment, the method includes forming a trench structure having first spacers on walls of the trench structure, a first sublithographic dimension being formed in a region between the first spacers situated on mutually opposite walls in at least one direction parallel to a wafer surface. The insulator layer is etched in a region between the first spacers situated on mutually opposite walls for forming a first passage hole, the first spacers being used as an etching mask. A layer made of an electrically conductive material is deposited at least over the first passage hole and partially etching back the layer made of the electrically conductive material in the first passage hole forming a first contact electrode.

Abstract: A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating layer and a semiconductive material are deposited in the deep trenches. The semiconductive material is recessed below a top surface of the workpiece. Shallow trenches are formed in the workpiece between adjacent second active areas, and an insulating material is deposited in the shallow trenches and in the semiconductive material recess. The deep trenches may also be formed between an adjacent first active area and second active area. The first active areas may be high voltage devices, and the second active areas may be low voltage devices. The shallow trench isolation over the recessed semiconductive material in the deep trenches is self-aligned.

Abstract: A semiconductor device having a memory array includes memory cells (101-104), a word line (42), a first bit line (68), and a second bit line (76). Within the memory array, the first and second bit lines (68 and 76) lie at different elevations above the word line (42). Local interconnects (58) are electrically connected to the first bit line (68) and some of the current carrying electrodes (48) in the memory array. The local interconnects (58) allow offset connections to be made. For floating gate memory cells (101-104) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (46 and 48) of a memory cell (101) to be programmed without significantly disturbing data in adjacent floating gate memory cells (102-104).

Abstract: A two transistor cell NOR architecture flash memory is provided wherein the floating gate transistor is couple between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.

Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).

Abstract: An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.