Patents by Inventor Danut Manea
Danut Manea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130250692Abstract: Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: ATMEL CORPORATIONInventors: Danut Manea, Erwin Castillon, Uday Mudumba, Sabina Centazzo, Stephen Trinh, Dixie Nguyen
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Publication number: 20110170354Abstract: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.Type: ApplicationFiled: March 21, 2011Publication date: July 14, 2011Applicant: ATMEL CORPORATIONInventors: Richard V. De Caro, Danut Manea
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Patent number: 7929356Abstract: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.Type: GrantFiled: September 5, 2008Date of Patent: April 19, 2011Assignee: Atmel CorporationInventors: Richard V. De Caro, Danut Manea
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Publication number: 20100061152Abstract: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.Type: ApplicationFiled: September 5, 2008Publication date: March 11, 2010Applicant: Atmel CorporationInventors: Richard V. De Caro, Danut Manea
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Patent number: 7242242Abstract: A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.Type: GrantFiled: March 29, 2006Date of Patent: July 10, 2007Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Patent number: 7236050Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.Type: GrantFiled: March 29, 2006Date of Patent: June 26, 2007Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Publication number: 20060170489Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.Type: ApplicationFiled: March 29, 2006Publication date: August 3, 2006Inventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Publication number: 20060170490Abstract: A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.Type: ApplicationFiled: March 29, 2006Publication date: August 3, 2006Inventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Patent number: 7084699Abstract: A current mirror comprising: a first current source; a first n-channel MOS transistor having a drain and a gate coupled to said current source and a source coupled to ground; a second n-channel MOS transistor having a drain, a gate coupled to said drain and said gate of said first n-channel MOS transistor, and a source coupled to ground; a third n-channel MOS transistor having a source coupled to said drain of said second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to ground, a source coupled to said second current source and said gate of said third n-channel MOS transistor, and a gate coupled to said drain and said gate of said first n-channel MOS transistor.Type: GrantFiled: April 7, 2005Date of Patent: August 1, 2006Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Publication number: 20050226051Abstract: A current mirror comprising: a first current source; a first n-channel MOS transistor having a drain and a gate coupled to said current source and a source coupled to ground; a second n-channel MOS transistor having a drain, a gate coupled to said drain and said gate of said first n-channel MOS transistor, and a source coupled to ground; a third n-channel MOS transistor having a source coupled to said drain of said second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to ground, a source coupled to said second current source and said gate of said third n-channel MOS transistor, and a gate coupled to said drain and said gate of said first n-channel MOS transistor.Type: ApplicationFiled: April 7, 2005Publication date: October 13, 2005Inventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
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Publication number: 20040056708Abstract: A current mirror comprises a current source; a first n-channel MOS transistor having a drain and a gate coupled to the current source and a source coupled to a source potential; a second n-channel MOS transistor having a drain, a gate coupled, to the drain and gate of the first n-channel MOS transistor, and a source coupled to the source potential; and a zero-threshold-voltage MOS transistor having a source coupled to the drain of the second n-channel MOS transistor, a gate coupled to the drain and the gate of the first n-channel MOS transistor, and a drain comprising an output-current node.Type: ApplicationFiled: April 3, 2003Publication date: March 25, 2004Applicant: Atmel Corporation, a Delaware CorporationInventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco