Patents by Inventor Darin A. Chan

Darin A. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978510
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: April 13, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
  • Publication number: 20190305041
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
  • Patent number: 10374005
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
  • Publication number: 20190206928
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAIVI layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
  • Patent number: 9825185
    Abstract: Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUDNRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Ming Zhu, Xinshu Cai, Fan Zhang, Danny Pak-Chum Shum, Darin Chan
  • Patent number: 9780231
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a handle layer. A partial buried insulator overlies the handle layer and underlies the active layer, terminates at a buried insulator termination point, and includes an electrically insulating material. A substrate extension is adjacent to the partial buried insulator, where the substrate extension overlies the handle layer and underlies the active layer, and where the substrate extension directly contacts the partial buried insulator at the buried insulator termination point. The substrate extension includes a semiconductive material. A memory gate overlies the active layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Ming Zhu, Danny Pak-Chum Shum, Xinshu Cai, Darin Chan
  • Patent number: 9698200
    Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Ming Zhu, Shunqiang Gong, Wanbing Yi, Darin Chan, Yiang Aun Nga
  • Publication number: 20170104029
    Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 13, 2017
    Inventors: Pinghui LI, Ming ZHU, Shunqiang GONG, Wanbing YI, Darin CHAN, Yiang Aun NGA
  • Patent number: 8293606
    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDARIES, Inc.
    Inventors: Sriram Madhavan, Qiang Chen, Darin A. Chan, Jung-Suk Goo
  • Publication number: 20110086484
    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
  • Patent number: 7880229
    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 1, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Sriram Madhavan, Qiang Chen, Darin A. Chan, Jung-Suk Goo
  • Patent number: 7861195
    Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 28, 2010
    Assignee: Advanced Mirco Devices, Inc.
    Inventors: Darin A. Chan, Yi Zou, Yuansheng Ma, Marilyn Wright, Mark Michael, Donna Michael, legal representative
  • Publication number: 20090193369
    Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Darin A. Chan, Yi Zou, Yuansheng Ma, Marilyn Wright, Mark Michael, Donna Michael
  • Publication number: 20090101976
    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
  • Patent number: 7494885
    Abstract: According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: February 24, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Darin A. Chan, Kei-Leong Ho, Lu You
  • Patent number: 7465623
    Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: December 16, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Darin A. Chan
  • Publication number: 20080305613
    Abstract: Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Mario M. PELELLA, Darin A. CHAN
  • Publication number: 20080124884
    Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.
    Type: Application
    Filed: August 28, 2006
    Publication date: May 29, 2008
    Inventors: Mario M. Pelella, Darin A. Chan
  • Patent number: 7276755
    Abstract: An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: October 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Darin A. Chan
  • Patent number: 7250667
    Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darin A. Chan, Simon Siu-Sing Chan, Paul L. King