Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.

Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

Abstract: Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions.

Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

Abstract: An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

Abstract: A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

Abstract: A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insulator layer. The metal connect is also in contact with a source of the device, thereby providing some electrical coupling between the source and the body, and as a result reducing or eliminating floating body effects in the device. A method of forming the metal interconnect includes etching away part of the buried insulator layer, for example by lateral etching or isotropic etching, and filling with metal, for example by chemical vapor deposition.

Abstract: A method of isolation of active islands on a silicon-on-insulator semiconductor device, including steps of (1) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; (2) etching through the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner; (3) rounding the at least one upper sharp corner of the active island, whereby at least one strained edge portion of the active island is formed; (4) removing at least a part of the at least one strained edge portion; and (5) at least partially filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure. An SOI wafer semiconductor device having a STI isolation structure free from a strained edge portion and a bird's beak.