Patents by Inventor Dario S. Filoteo, Jr.
Dario S. Filoteo, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9281300Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.Type: GrantFiled: September 15, 2010Date of Patent: March 8, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, Jr., Rachel L. Abinan
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Patent number: 9034693Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.Type: GrantFiled: September 28, 2011Date of Patent: May 19, 2015Assignee: ST ASSEMBLY TEST SERVICES LTD.Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
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Patent number: 9000579Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.Type: GrantFiled: March 30, 2007Date of Patent: April 7, 2015Assignee: STATS ChipPAC Ltd.Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Emmanuel Espiritu, Rachel Layda Abinan
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Patent number: 8421221Abstract: An integrated circuit heat spreader stacking system includes: an integrated circuit on a substrate; a heat spreader having a heat sink dome; a stacking stand-off for the heat spreader; and the heat spreader mounted with the heat sink dome over the integrated circuit.Type: GrantFiled: May 17, 2010Date of Patent: April 16, 2013Assignee: STATS ChipPAC Ltd.Inventors: Dario S. Filoteo, Jr., Emmanuel Espiritu, Philip Lyndon Cablao
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Patent number: 8395254Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.Type: GrantFiled: March 30, 2006Date of Patent: March 12, 2013Assignee: STATS Chippac Ltd.Inventors: Emmanuel Espiritu, Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Rachel Layda Abinan, Allan Ilagan
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Patent number: 8138080Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.Type: GrantFiled: March 10, 2006Date of Patent: March 20, 2012Assignee: Stats Chippac Ltd.Inventors: Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
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Publication number: 20120018886Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.Type: ApplicationFiled: September 28, 2011Publication date: January 26, 2012Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, JR.
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Patent number: 8097935Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: GrantFiled: February 10, 2010Date of Patent: January 17, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, Jr.
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Patent number: 8097496Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: GrantFiled: February 10, 2010Date of Patent: January 17, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, Jr.
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Patent number: 8030783Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.Type: GrantFiled: October 20, 2009Date of Patent: October 4, 2011Assignee: St Assembly Test Services Ltd.Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
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Patent number: 8026129Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.Type: GrantFiled: March 10, 2006Date of Patent: September 27, 2011Assignee: STATS ChipPAC Ltd.Inventors: Philip Lyndon Cablao, Dario S. Filoteo, Jr., Leo A. Merilo, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
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Patent number: 8021931Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.Type: GrantFiled: November 20, 2007Date of Patent: September 20, 2011Assignee: Stats Chippac, Inc.Inventors: Dario S. Filoteo, Jr., Emmanuel A. Espiritu
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Patent number: 7928564Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: GrantFiled: September 24, 2008Date of Patent: April 19, 2011Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon
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Patent number: 7911046Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.Type: GrantFiled: February 24, 2009Date of Patent: March 22, 2011Assignee: Stats Chippac Ltd.Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Jr., Allan P. Ilagan
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Publication number: 20110001240Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.Type: ApplicationFiled: September 15, 2010Publication date: January 6, 2011Applicant: STATS CHIPPAC, LTD.Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, JR., Rachel L. Abinan
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Patent number: 7863730Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.Type: GrantFiled: August 18, 2004Date of Patent: January 4, 2011Assignee: ST Assembly Test Services Ltd.Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Diane Sahakian, Seng Guan Chow, Dario S. Filoteo, Jr., Virgil Cotoco Ararao
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Publication number: 20100224991Abstract: An integrated circuit heat spreader stacking system includes: an integrated circuit on a substrate; a heat spreader having a heat sink dome; a stacking stand-off for the heat spreader; and the heat spreader mounted with the heat sink dome over the integrated circuit.Type: ApplicationFiled: May 17, 2010Publication date: September 9, 2010Inventors: Dario S. Filoteo, JR., Emmanuel Espiritu, Philip Lyndon Cablao
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Patent number: 7786575Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.Type: GrantFiled: December 4, 2009Date of Patent: August 31, 2010Assignee: STATS ChipPAC Ltd.Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Jr., Emmanuel A. Espiritu, Leo A. Merilo
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Patent number: 7759169Abstract: An integrated circuit heat spreader stacking system is provided including mounting an integrated circuit on a substrate, forming a heat spreader, forming a stacking stand-off for the heat spreader, and mounting a heat spreader over the integrated circuit.Type: GrantFiled: July 11, 2006Date of Patent: July 20, 2010Assignee: Stats Chippac Ltd.Inventors: Dario S. Filoteo, Jr., Emmanuel Espiritu, Philip Lyndon Cablao
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Publication number: 20100140761Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, JR.