Patents by Inventor Darrell M. Erb

Darrell M. Erb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7157795
    Abstract: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of ?-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: January 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven C. Avanzino, Christy Mei-Chu Woo
  • Patent number: 7132363
    Abstract: Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Yang, Darrell M. Erb, Fei Wang
  • Patent number: 7071564
    Abstract: The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of ?-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the ?-Ta layer and a layer of ?-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of ?-Ta at a thickness of 25 ? to 40 ?, depositing a layer of tantalum nitride at a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with ?-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven Avanzino, Christy Mei-Chu Woo
  • Patent number: 6979625
    Abstract: High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 27, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Connie Pin-Chin Wang, Darrell M. Erb
  • Patent number: 6869878
    Abstract: The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: March 22, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ercan Adem, John E. Sanchez, Darrell M. Erb, Suzette K. Pangrle
  • Patent number: 6831003
    Abstract: For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Pin-Chin C. Wang, Darrell M. Erb
  • Patent number: 6768204
    Abstract: The present invention provides for improved alignment of an opening in a lower dielectric layer with an opening in an upper dielectric layer. This improved alignment is beneficial as it improves the functionality of devices with dual damascene material arrangements, as normal misalignments do not deem the devices inferior or non-functional. Further, the present invention is beneficial as it allows for a designer, such as a microprocessor designer, to depend on more predictable conductive characteristics of contacts between a first conductive region and a second conductive region.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: July 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd P. Lukanc, Fei Wang, Darrell M. Erb
  • Patent number: 6756303
    Abstract: A conductive diffusion barrier surrounding a conductive element is enhanced by an implanted diffusion barrier enhancing material. The enhancing material is implanted using a low energy implant at an angle to the substrate, such that the portion of the diffusion barrier at the bottom of the conductive element is protected during implantation. This prevents the increased resistivity caused by the enhancing material from affecting the conductive path between the conductive element and another conductive element. The diffusion barrier is preferably titanium nitride (TiN) and the enhancing material is preferably silicon (Si).
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Fei Wang
  • Patent number: 6756306
    Abstract: The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Darrell M. Erb
  • Patent number: 6727592
    Abstract: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: April 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, John E. Sanchez, Darrell M. Erb, Amit P. Marathe
  • Patent number: 6717266
    Abstract: The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Marathe, Darrell M. Erb
  • Patent number: 6689689
    Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: February 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Darrell M. Erb, Sergey Lopatin
  • Publication number: 20040023511
    Abstract: The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
    Type: Application
    Filed: December 30, 2002
    Publication date: February 5, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Darrell M. Erb
  • Publication number: 20030218253
    Abstract: A precursor of a low-k porous dielectric is applied to an integrated circuit substrate. The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Wiring elements are then inlaid in the low-k dielectric matrix. After the wiring elements are formed, remaining porogen is decomposed to leave pores in the low-k dielectric matrix. The resulting wiring elements are smooth walled.
    Type: Application
    Filed: December 13, 2001
    Publication date: November 27, 2003
    Inventors: Steven C. Avanzino, Darrell M. Erb, Fei Wang, Sergey Lopatin
  • Publication number: 20030219968
    Abstract: A nonporous sacrificial layer is used to form conductive elements such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth walled conductive elements, the sacrificial layer is removed and replaced with a porous dielectric, resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials.
    Type: Application
    Filed: December 13, 2001
    Publication date: November 27, 2003
    Inventors: Ercan Adem, Darrell M. Erb
  • Patent number: 6500754
    Abstract: An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: December 31, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven C. Avanzino, Alline F. Myers
  • Patent number: 6465889
    Abstract: The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide capping layer/BARC having an extinction coefficient (k) of about −0.2 to about −0.5, without the need for a middle etch stop layer, thereby improving efficiency by reducing the number of processing steps.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: October 15, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Fei Wang, Lynne A. Okada, Calvin T. Gabriel, Darrell M. Erb
  • Publication number: 20020140101
    Abstract: Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid misalignment problems. Embodiments further include dual damascene processing using Cu metallization.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 3, 2002
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kai Yang, Darrell M. Erb, Fei Wang
  • Patent number: 6454916
    Abstract: A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: September 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, Steven C. Avanzino, Darrell M. Erb
  • Patent number: 6455425
    Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Darrell M. Erb, Sergey Lopatin