Abstract: The present invention relates to a system for wireless control of home media sources that utilizes a home digital network to transport packetized IR transmitter data to a remote location. The system allows for flexible control of multiple devices that accept IR commands without requiring additional wiring, and is independent of any particular IR protocol.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: The present invention relates to a system for wireless control of home media sources that utilizes a home digital network to transport packetized IR transmitter data to a remote location. The system allows for flexible control of multiple devices that accept IR commands without requiring additional wiring, and is independent of any particular IR protocol.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information. An artificial time stamp module and a data transport device can be used to generate the pseudo MPEG information, including associating an artificial time stamp with the digital video information. This pseudo MPEG information can be decoded as MPEG information.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A method, system, and a computer program product for filtering palettized image formats are presented. In an embodiment, data is retrieved from a palette of an image. Data associated with a channel of the palette is filtered, and stored, for example, together with a pixel buffer of the image to form a filtered image. Additionally, a method, system, and a computer program product for displaying images stored in a modified palettized image format are presented. In an embodiment, data is retrieved from a palette and from a pixel buffer of an image stored in modified palettized image format. Filtered pixels of the image are formed by combining, for each pixel in the pixel buffer, data retrieved from the palette with filtered data, retrieved from the pixel buffer. The modified palettized image is rendered on a display by displaying the filtered pixels.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information. An artificial time stamp module and a data transport device can be used to generate the pseudo MPEG information, including associating an artificial time stamp with the digital video information. This pseudo MPEG information can be decoded as MPEG information.

Abstract: Herein described is a system and method for improving the appearance of video by generating an improved 4:2:2 chroma. The system comprises a 4:2:2 to 4:2:0 chroma regenerator that regenerates 4:2:0 chroma given a received 4:2:2 chroma, and a 4:2:0 to 4:2:2 chroma generator that weaves and interpolates the regenerated 4:2:0 chroma to yield an adjusted 4:2:2 chroma. The system further comprises a blending system used for blending the adjusted 4:2:2 chroma with the received 4:2:2 chroma based on a control input provided by a motion indication signal. The method comprises regenerating a 4:2:0 chroma from a received 4:2:2 chroma using an algorithm. The method further comprises generating an adjusted 4:2:2 chroma using the regenerated 4:2:0 chroma using another algorithm. The method further comprises blending the adjusted 4:2:2 chroma with the received 4:2:2 chroma to generate an improved 4:2:2 chroma.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information received at a digital video input. An artificial time stamp module is used to generated the pseudo MPEG information from associating an artificial time stamp with the digital video information. This pseudo MPEG information is received, for example, at an MPEG signal processor in a set-top box. The MPEG signal processor decodes the pseudo MPEG information and outputs the decoded MPEG information under control of the artificial time stamps.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: An audio calibration system includes control logic, an input device, a display, a noise generator, an inverter, a plurality of speakers, and a delay module coupled to each speaker. Upon receipt of a calibration start signal from the input device, the control logic directs the noise generator to produce substantially random noise which is then provided through the delay modules to each speaker. The inverter inverts the random signal to one of the speakers. Thus, in a two speaker system the sound emanating from one of the speakers is an inverted version of the sound emanating from the other speaker. At the points where the sound from each speaker combine, a “null” line is created as the two sources of sound cancel one another. The control logic controls the amount of delay introduced by each delay module into the sound provided to each speaker. By varying the amount of the time delay, the control logic can control the position of the null line to coincide with a listener's desired listening location.

Abstract: A video decoding system includes an embedded microcontroller that provides memory arbitration in addition to processing and control functions. The microcontroller architecture provides a first-in, first-out (FIFO) queue for storing memory access instructions and a processing logic for executing software instructions. The microcontroller processing logic determines which components within the decoding system need access to memory and stores a sequence of memory access instructions into the FIFO queue. Each memory access instruction is associated with one decoder component. When main memory becomes available, a memory access instruction is dequeued from the FIFO and transmitted to the associated decoder component, which is then permitted to access memory. The microcontroller receives indicator signals from the decoder components that indicate when the decoder components have finished accessing memory and, thus, when the memory device is available for subsequent transactions.

Abstract: The present invention relates to a system for wireless control of home media sources that utilizes a home digital network to transport packetized IR transmitter data to a remote location. The system allows for flexible control of multiple devices that accept IR commands without requiring additional wiring, and is independent of any particular IR protocol.

Abstract: A circuit for freezing a video frame having a first field interlaced with a second field. The circuit generally comprises a memory and a filter. The memory may be configured to present a plurality of coefficient signals that define (i) a first coefficient set for the first field and (ii) a second coefficient set for the second field. The filter may be configured to present a new frame in place of the video frame. The new frame may be generated from either (i) the first field and the first coefficient set in response to freezing on the first field or (ii) the second field and the second coefficient set in response to freezing on the second field.

Abstract: An optical disk system is presented which stores disk- and user-specific settings, along with an associated method. The optical disk system includes a disk drive unit for retrieving identification data and encoded video data stored upon an optical disk, an input device for inputting user settings, and a microprocessor memory unit having a non-volatile portion for storing the identification data and the user settings. Information specific to optical disks (e.g., DVDs) and users is stored within the non-volatile portion of the microprocessor memory unit. The user settings may include, for example, spoken language, video display format, audio volume setting, and subtitle language. The user settings may be retrieved and invoked, conveniently allowing a user to view a presentation (e.g., a movie), or to continue viewing an interrupted presentation, without having to reselect viewing and listening preferences. The identification data may include a portion of a title of the optical disk.

Abstract: A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage which provides the output filtered image from the filter unit. As such, the video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter.

Abstract: A video decoder decimates an input image to produce a decimated output image. The video decoder uses approximately every line of pixels in the input image to compute the lines of pixels in the decimated image. The video decoder includes a vertical decimation filter that computes an average, and preferably a weighted average, of luminance (luma) values associated with pixels from each of four lines in the input image. The decimation filter preferably computes a weighted average of lumas from four adjacent lines of pixels from the input image which may represent a frame or a field of video data. The weighted average preferably uses coefficients that weight each luma in the calculation differently. After calculating all of the luma values for a particular line of the decimated image, the line number associated with the first of the four adjacent lines is incremented by four (in a field-based system) to determine the initial line number for calculating the next line in the decimated image.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal and a first feedback signal. The second circuit may be configured to generate an output signal in response to the intermediate signal and a second feedback signal. The third circuit may be configured to generate the first feedback signal and the second feedback signal in response to the output signal.