Abstract: A square estimator computes an estimate of the square of an input number. The input number preferably is provided to combinational logic that logically manipulates the bits of the input number to generate an estimate of the square of the input number. The level of accuracy of the square generator can be programmed or predetermined by including or enabling various term generator logic units. Each term generator logic unit produces an output value that, when added to all of the other output values from the other term generators, provides an estimate of the square of the input number. Additionally, negative correction logic can also be incorporated into the square estimator for producing a negative correction value that when added to the estimate values from the various term generators, permits the square estimator to estimate the square of negative numbers as well as positive numbers.

Abstract: A bubble producing assembly has a frame having a handle section and an opening, a fan positioned inside the opening, and a bubble producing device positioned above the fan and extending over the opening. The bubble producing device has a primary loop having an enclosing edge that defines an interior opening, with the primary loop disposed at a first vertical level. The bubble producing device also includes a plurality of secondary loops disposed at a second vertical level that is different from the first vertical level, the secondary loops positioned with respect to the primary loop such that the secondary loops extend into the space defined by the interior opening. In a preferred embodiment, the secondary loops are smaller in size than the primary loop.

Abstract: An audio decoder is described which supports simple sound-effect generation. The audio decoder includes a direct access pulse code modulation (PCM) first-in-first-out buffer (FIFO) to support simple sound effect generation. In one embodiment, the audio decoder additionally includes an input buffer, a decoding module, and an output interface. The input buffer buffers incoming data frames for the decoding module to retrieve and convert to a sequence of decoded audio samples. The FIFO is configured to receive and buffer audio sound effect samples from a control component external to the audio decoder. The output interface is configurable to retrieve decoded audio samples from the decoding module and audio sound effect samples from the FIFO. Any retrieved audio sound effect samples are included in a digital audio output signal provided by the output interface. The digital audio output signal may be provided directly to a digital-to-analog converter for sound reproduction.

Abstract: A system and method for synchronizing a decoded, interlaced-field data stream with an interlaced field display. A system for displaying an MPEG encoded data stream includes an MPEG decoder which converts the encoded data stream into a sequence of frames. Each frame has an associated top field, bottom field, top-field-first flag, and repeat-first-field flag. The system also includes a display processor which receives the flags and determines a field display sequence for each frame which conforms to an overall display sequence which strictly alternates between top and bottom fields. This strict alternation in enforced even when the decoded field sequence does not adhere to a strict alternation. The system achieves this result with a worst-case temporal distortion of one field by inserting or omitting a 3:2 pulldown frame at each broken alternation point.

Abstract: In an MPEG audio and video signal transmission system in which audio and video signals are encoded in packets which are multiplexed to form a stream for transmission, a receiver system includes a demultiplexer to separate audio and video packets. The header for each packet is parsed, and an error propagation header is inserted with each packet to identify byte count of the packet and an error flag. In a preferred embodiment the error propagation header includes a first byte representing the total byte count and a single bit in a second byte as the error flag. The error propagation header allows errors to be accurately located even in the presence of variable delay introduced by buffers.

Abstract: A CMOS oscillator is disclosed using an inverter in which a pair of control terminals are employed to invoke various sized devices which control the flow of current. The inverter gain is determined by the size of the CMOS devices employed. A tuned circuit coupled to the inverter causes it to oscillate at the frequency of parallel resonance. The control terminals are coupled to the inverter invoke transistors that are sized as desired to establish the current flow and gain in the inverter. The current flow is controlled to optimize the gain of the inverter in terms of the frequency of oscillation. A Schmitt trigger can be employed to clean up the oscillator output for digital clock source applications.