Patents by Inventor Darryl G. Walker

Darryl G. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497430
    Abstract: A semiconductor device powered by a first power supply potential, can include a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating a predetermined voltage window in which the first power supply potential is located; an assist control circuit configured to provide at least one assist signal in response to the at least one voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell, as compared to the read or write operations without the at least one assist signal.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Darryl G. Walker
  • Patent number: 10453823
    Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be electrically connected to a first terminal, which is electrically connected to receive a power supply potential from a power supply terminal. The second semiconductor device can receive the power supply potential from the power supply terminal. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The first capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Darryl G. Walker
  • Patent number: 10418346
    Abstract: A multi-chip stack can include a first semiconductor device disposed between a plurality of electrical connections and the second semiconductor device. The first semiconductor device can include a first through via and a first electrostatic discharge (ESD) protection circuit connected to a first one of the electrical connections. The first ESD Protection circuit can have a first ESD protection structure. The first through via provides an electrical connection through the first semiconductor device from a first surface to an opposite surface of the first semiconductor device and between the first one of the plurality of electrical connections and a first terminal of the first circuit. The first terminal of the first circuit can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure formed on the second semiconductor device.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 17, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10403384
    Abstract: A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 3, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10365318
    Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Inventor: Darryl G. Walker
  • Publication number: 20190130988
    Abstract: A semiconductor device has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist disable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device when at an assist enable logic level as compared to the read or write operation when the assist signal has the assist disable logic level.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 2, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10262975
    Abstract: A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10260962
    Abstract: A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10262976
    Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Publication number: 20190074055
    Abstract: A method of operating a semiconductor device powered by a first power supply potential can include generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read or write assist signal having a read or write assist enable logic level in response to the first latched voltage signal; and altering a read or write operation to a static random access memory (SRAM) cell in response to the at least one read or write assist signal having the read or write assist enable logic level as compared to when the at least one read or write assist signal has a read or write assist disable logic level.
    Type: Application
    Filed: October 27, 2018
    Publication date: March 7, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10177121
    Abstract: A system can include a first semiconductor device, a second semiconductor device and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be coupled to receive a power supply potential. At least one conductive data path is coupled between the first semiconductor memory device and the second semiconductor device.
    Type: Grant
    Filed: September 15, 2018
    Date of Patent: January 8, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10163524
    Abstract: A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 25, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10141058
    Abstract: A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: November 27, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10134720
    Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 20, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10128215
    Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 13, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10115710
    Abstract: A package can include a number of stacked dynamic random access memory (DRAM) semiconductor devices and an interposer. Wirings can be formed in the interposer to provide electric connections essentially orthogonal between the first and second surfaces of the interposer to external connections. Through vias can provide electrical connections between surfaces of the DRAM semiconductor devices, and interface connections can provide electrical connections between through vias of adjacent DRAM semiconductor devices. External connections can receive a power supply potential and a data signal.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 30, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10115455
    Abstract: A method of operating a semiconductor device can include determining in which of a plurality of voltage windows the first power supply potential is located; changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows; detecting a change in the at least one voltage window signal; and generating at least one read assist signal in response to the at least one voltage window signal; wherein the at least one read assist signal alters a read operation to a static random access memory (SRAM) cell, as compared to the read operation without the at least one read assist signal.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 30, 2018
    Inventor: Darryl G. Walker
  • Publication number: 20180306854
    Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventor: Darryl G. Walker
  • Publication number: 20180245989
    Abstract: A method of operating a semiconductor device can include providing a multi-bit count value to a temperature sensing circuit; and generating an output having a detect logic level from the temperature sensing circuit based on an internal temperature of the semiconductor device and the count value. In some embodiments, a semiconductor device can be a dynamic random access memory (DRAM) device.
    Type: Application
    Filed: April 28, 2018
    Publication date: August 30, 2018
    Inventor: Darryl G. Walker
  • Publication number: 20180233195
    Abstract: A method of operating a semiconductor device can include determining in which of a plurality of voltage windows the first power supply potential is located; changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows; detecting a change in the at least one voltage window signal; and generating at least one read assist signal in response to the at least one voltage window signal; wherein the at least one read assist signal alters a read operation to a static random access memory (SRAM) cell, as compared to the read operation without the at least one read assist signal.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventor: Darryl G. Walker