Abstract: A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.

Abstract: A method of operating a semiconductor device powered by a first power supply potential can include generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read or write assist signal having a read or write assist enable logic level in response to the first latched voltage signal; and altering a read or write operation to a static random access memory (SRAM) cell in response to the at least one read or write assist signal having the read or write assist enable logic level as compared to when the at least one read or write assist signal has a read or write assist disable logic level.

Abstract: A system can include a first semiconductor device, a second semiconductor device and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be coupled to receive a power supply potential. At least one conductive data path is coupled between the first semiconductor memory device and the second semiconductor device.

Abstract: A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.

Abstract: A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: A package can include a number of stacked dynamic random access memory (DRAM) semiconductor devices and an interposer. Wirings can be formed in the interposer to provide electric connections essentially orthogonal between the first and second surfaces of the interposer to external connections. Through vias can provide electrical connections between surfaces of the DRAM semiconductor devices, and interface connections can provide electrical connections between through vias of adjacent DRAM semiconductor devices. External connections can receive a power supply potential and a data signal.

Abstract: A method of operating a semiconductor device can include determining in which of a plurality of voltage windows the first power supply potential is located; changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows; detecting a change in the at least one voltage window signal; and generating at least one read assist signal in response to the at least one voltage window signal; wherein the at least one read assist signal alters a read operation to a static random access memory (SRAM) cell, as compared to the read operation without the at least one read assist signal.

Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.

Abstract: A method of operating a semiconductor device can include providing a multi-bit count value to a temperature sensing circuit; and generating an output having a detect logic level from the temperature sensing circuit based on an internal temperature of the semiconductor device and the count value. In some embodiments, a semiconductor device can be a dynamic random access memory (DRAM) device.

Abstract: A method of operating a semiconductor device can include determining in which of a plurality of voltage windows the first power supply potential is located; changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows; detecting a change in the at least one voltage window signal; and generating at least one read assist signal in response to the at least one voltage window signal; wherein the at least one read assist signal alters a read operation to a static random access memory (SRAM) cell, as compared to the read operation without the at least one read assist signal.

Abstract: A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.

Abstract: A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply potential and to provide a first and second voltage window signal by comparing the first potential to a first and second reference potential. The voltage window signals indicate voltage windows in which the first power supply potential is located. An assist control circuit receives the voltage window signals and provides at least one assist signal which can alter read or write operations to a static random access memory cell.

Abstract: A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window signal, the voltage window signal indicates a predetermined voltage window in which a potential of the first power supply potential is located; latching the at least one voltage window signal to provide at least one latched voltage window signal; and generating at least one assist signal in response to at least one latched voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal.

Abstract: A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

Abstract: A multi-chip device can include stacked semiconductor devices including a top and bottom semiconductor device. The top semiconductor device can include a first circuit. The bottom semiconductor device can include a first through via and a first ESD protection circuit electrically connected to an external electrical connection of the device. The first ESD protection circuit can include a first ESD protection structure. The first through via can provide an electrical connection through the bottom semiconductor device between the external electrical connection and a first terminal of the first circuit, which can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure.

Abstract: A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

Abstract: A method can of operating a semiconductor device can include generating a read or write assist signal having an enable logic level in response to a power supply potential being in a first voltage window and a disable logic level in response to the power supply potential being in a second voltage window. Access operations to a static random access memory (SRAM) cell can be altered in response to the assist signal having the assist enable logic level. The second voltage window can be larger than the first voltage window.

Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.