Patents by Inventor Darryl J. McKenney

Darryl J. McKenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096915
    Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 9, 2018
    Assignee: MERCURY SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Absu Methratta, Erica Ouellette
  • Patent number: 9761972
    Abstract: An RF connector includes a conductive pin for carrying an RF signal. The conductive pin has a first longitudinal end that serves to interface with a male RF connector to receive the RF signal. The pin also includes a second longitudinal end for connecting with a printed circuit board (PCB). The second longitudinal end may be tapered, and the pin may have a groove formed above the tapered end. A housing encircles the conductive pin. The housing is shaped and sized to accept the male RF connector. A grounding element may be positioned on the bottom of the housing. The grounding element is to contact the PCB when the connector is connected to the PCB. The grounding element may be ring-shaped and soldered to the housing or epoxied to the housing.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 12, 2017
    Assignee: MERCURY SYSTEMS, INC.
    Inventors: Philip Beucler, Daniel Coolidge, Darryl J. McKenney, Kevin Jorczak
  • Publication number: 20170244184
    Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 24, 2017
    Inventors: Darryl J. MCKENNEY, Absu METHRATTA, Erica OUELLETTE
  • Publication number: 20170149154
    Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventors: Darryl J. MCKENNEY, Absu METHRATTA, Erica OUELLETTE
  • Publication number: 20170149155
    Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation from the surface interconnect during the soldering process. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Darryl J. MCKENNEY, Absu METHRATTA, Erica OUELLETTE
  • Publication number: 20170149156
    Abstract: An RF connector includes a conductive pin for carrying an RF signal. The conductive pin has a first longitudinal end that serves to interface with a male RF connector to receive the RF signal. The pin also includes a second longitudinal end for connecting with a printed circuit board (PCB). The second longitudinal end may be tapered, and the pin may have a groove formed above the tapered end. A housing encircles the conductive pin. The housing is shaped and sized to accept the male RF connector. A grounding element may be positioned on the bottom of the housing. The grounding element is to contact the PCB when the connector is connected to the PCB. The grounding element may be ring-shaped and soldered to the housing or epoxied to the housing.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 25, 2017
    Inventors: Philip BEUCLER, Daniel COOLIDGE, Darryl J. MCKENNEY, Kevin JORCZAK
  • Patent number: 9389654
    Abstract: Various embodiments provide a circuit board module include a primary cover, a secondary cover and a circuit board sandwiched between the primary cover and the secondary cover. A first set of fins or channels may be provided on a surface of the primary cover. The first set of fins or channels guide cooling air flowing on the surface of the primary cover. A second set of fins or channels may be provided on a surface of the second cover. The second set of fins or channels guide the cooling air flowing on the surface of the secondary cover. The second set of fins or channels intermates with the first set of fins or channels to form a sealed casing enclosing the circuit board. The sealed casing forms a Faraday cage to protect the circuit board from electromagnetic interference.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 12, 2016
    Assignee: MERCURY SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Paul Zuidema, Donald Blanchet, Daniel Coolidge
  • Patent number: 9128679
    Abstract: According to exemplary embodiments, a controlled-depth slot extending into a circuit board is provided. The controlled depth slot may be milled, and may comprise ½ radial plated through-holes to generate a solderable “D” interconnect feature. The slot may include interconnect features on one to five sides. According to another exemplary embodiment, a circuit board having a depth-controlled interconnect slot is provided in conjunction with one or more solderable technology modules. The one or more solderable technology modules may include memory devices, power devices such as Point of Load Supplies (POLS), security devices and anti-tamper devices, capacitance devices, and other types of chips such as Field Programmable Gate Arrays (FPGAs). The solderable technology modules may be soldered into the slot to secure the modules in the slot and connect the modules to interconnects on the circuit board.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 8, 2015
    Assignee: MERCURY COMPUTER SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Daniel Toohey, Stephen Mariani, Michael Gust, Absu Methratta, Timothy Fleury, Steven Imperalli
  • Patent number: 9033750
    Abstract: An electrical contact is provided for mating with a mating contact. The electrical contact includes a base extending a length along a central longitudinal axis, and an arm extending a length outward from the base along the central longitudinal of the base. The arm includes a first mating bump and a second mating bump. The first and second mating bumps have respective first and second mating surfaces. The arm is configured to engage the mating contact at each of the first and second mating surfaces to establish an electrical connection with the mating contact. The first mating surface of the first mating bump is spaced apart along the length of the arm from the second mating surface of the second mating bump.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 19, 2015
    Assignees: TYCO ELECTRONICS CORPORATION, MERCURY SYSTEMS, INC.
    Inventors: Keith Edwin Miller, Chong Hun Yi, Matthew Richard McAlonis, Kevin Thackston, Dustin Carson Belack, Albert Tsang, Nicholas Paul Ruffini, Darryl J. McKenney, Erica L. Ouellette
  • Publication number: 20140160670
    Abstract: Various embodiments provide a circuit board module include a primary cover, a secondary cover and a circuit board sandwiched between the primary cover and the secondary cover. A first set of fins or channels may be provided on a surface of the primary cover. The first set of fins or channels guide cooling air flowing on the surface of the primary cover. A second set of fins or channels may be provided on a surface of the second cover. The second set of fins or channels guide the cooling air flowing on the surface of the secondary cover. The second set of fins or channels intermates with the first set of fins or channels to form a sealed casing enclosing the circuit board. The sealed casing forms a Faraday cage to protect the circuit board from electromagnetic interference.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 12, 2014
    Applicant: MERCURY COMPUTER SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Paul Zuidema, Donald Blanchet, Daniel Coolidge
  • Publication number: 20140051294
    Abstract: An electrical contact is provided for mating with a mating contact. The electrical contact includes a base extending a length along a central longitudinal axis, and an arm extending a length outward from the base along the central longitudinal of the base. The arm includes a first mating bump and a second mating bump. The first and second mating bumps have respective first and second mating surfaces. The arm is configured to engage the mating contact at each of the first and second mating surfaces to establish an electrical connection with the mating contact. The first mating surface of the first mating bump is spaced apart along the length of the arm from the second mating surface of the second mating bump.
    Type: Application
    Filed: January 16, 2013
    Publication date: February 20, 2014
    Applicants: MERCURY SYSTEMS, INC., TYCO ELECTRONICS CORPORATION
    Inventors: Keith Edwin Miller, Chong Hun Yi, Matthew Richard McAlonis, Kevin Thackston, Dustin Carson Belack, Albert Tsang, Nicholas Paul Ruffini, Darryl J. McKenney, Erica L. Ouellette
  • Publication number: 20130058050
    Abstract: According to exemplary embodiments, a controlled-depth slot extending into a circuit board is provided. The controlled depth slot may be milled, and may comprise ½ radial plated through-holes to generate a solderable “D” interconnect feature. The slot may include interconnect features on one to five sides. According to another exemplary embodiment, a circuit board having a depth-controlled interconnect slot is provided in conjunction with one or more solderable technology modules. The one or more solderable technology modules may include memory devices, power devices such as Point of Load Supplies (POLS), security devices and anti-tamper devices, capacitance devices, and other types of chips such as Field Programmable Gate Arrays (FPGAs). The solderable technology modules may be soldered into the slot to secure the modules in the slot and connect the modules to interconnects on the circuit board.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: MERCURY COMPUTER SYSTEMS, INC.
    Inventors: Darryl J. MCKENNEY, Daniel TOOHEY, Stephen MARIANI, Michael GUST, Absu METHRATTA, Timothy FLEURY, Steven IMPERALLI
  • Publication number: 20080280463
    Abstract: Improved printed circuit boards (PCBs), printed circuit board assemblies (PCBAs) and methods thereof contemplate PCBs with recesses incorporated into planar surfaces thereof adapted to receive respective elongate leads of circuit components. The recesses are sized so as to prevent distal ends of the leads from emerging through the far sides of the boards and, indeed, allow for positioning of the component flush with, or offset above, the board to which they are mounted.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: MERCURY COMPUTER SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Michael W. Gust, David G. Persad
  • Publication number: 20040040148
    Abstract: A novel process is provided for the high speed fabrication of flexible printed circuit boards in continuous roll form and at a cost which is substantially less than the cost of existing fabrication processes. A web of substrate material is supplied from a roll and one or both surfaces are sputter coated with a tie-coat of Monel or chrome and a copper seed layer. The tie-coat is typically of a thickness of about 50-300 angstroms, and the copper seed layer has a thickness of about 200-4000 angstroms. Plated through holes are provided for double sided printed circuit boards, the holes being provided by laser or other suitable drilling equipment in an intended pattern on the substrate. A plating mask is provided with a negative image to allow subsequent selective electrodeposition of copper onto the unmasked areas of the substrate surfaces. The web is then passed through a continuous copper plating cell which provides a plate-up of copper on the unmasked areas of the seed layer.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Applicant: PARLEX CORPORATION
    Inventors: Arthur DeMaso, Darryl J. McKenney, Laurea J. Doiron
  • Patent number: 6689958
    Abstract: A flat ribbon cable having a controlled impedance and suitable for use at high data rates. The ribbon cable includes a plurality of conductors arranged side-by-side within an insulating material. The conductors include a first portion at each end having a generally circular cross-section, a center portion of generally rectangular cross-section in which the width is greater than the height and a transition portion at each end between the first portion and the second portion. A shield is disposed over selected ones of the plurality of conductors on at least one side of the ribbon cable. A drain wire is provided that is conductively coupled to the shield and may be disposed between the shield and insulating material. The drain wire is disposed over one of the conductors and may be conductively coupled to the conductor via use of a single contact of an insulation displacement connector that engages both the drain wire and the respective conductor.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: February 10, 2004
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Steven J. Bibeau, Laurea J. Doiron, Jr.
  • Publication number: 20040011553
    Abstract: A flat multi-conductor cable and a method for manufacturing such a cable to maintain consistent spacing between adjacent conductors. A dielectric film is laminated to both sides of a plurality of conductors, such as flat copper conductors. The film is heated to cause the film to flow around and adhere to the conductors. A jacket is extruded around the dielectric film to form a jacketed multi-conductor cable. A conductive shield may be applied over the dielectric film prior to the extrusion of the cable jacket. The conductive shield may be conductively coupled to one or more of the conductors by dimpling the shield over the respective conductors or by a laser ablation technique.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Applicant: Parlex Corporation
    Inventors: David Cianciolo, Darryl J. McKenney, Arthur DeMaso, Laurea J. Doiron, Steven J. Bibeau
  • Publication number: 20040011552
    Abstract: A flat ribbon cable having a controlled impedance and suitable for use at high data rates. The ribbon cable includes a plurality of conductors arranged side-by-side within an insulating material. The conductors include a first portion at each end having a generally circular cross-section, a center portion of generally rectangular cross-section in which the width is greater than the height and a transition portion at each end between the first portion and the second portion. A shield is disposed over selected ones of the plurality of conductors on at least one side of the ribbon cable. A drain wire is provided that is conductively coupled to the shield and may be disposed between the shield and insulating material. The drain wire is disposed over one of the conductors and may be conductively coupled to the conductor via use of a single contact of an insulation displacement connector that engages both the drain wire and the respective conductor.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Applicant: Parlex Corporation
    Inventors: Darryl J. McKenney, Steven J. Bibeau, Laurea J. Doiron
  • Patent number: 6645549
    Abstract: A process for providing bond enhancement and an etch resist for a printed circuit board is provided. A sheet comprising at least a layer of copper is immerses in a first immersion tin solution comprising a tin metal and a complexing agent in an acidic medium for a time sufficient to deposit a first heavy tin deposit on the sheet. The sheet is then immersed in a second immersion tin solution comprising stannous tin ions and stannic tin ions and a complexing agent in an acidic medium for a time sufficient to deposit a second thin tin deposit on the sheet. The second thin tin deposit has a thickness less than a thickness of the first heavy tin deposit. A rough surface texture providing mechanical adhesion sites results. The board is then treated with a coupling agent, such as silane, for enhanced bonding to a subsequent epoxy or other polymer prepreg. Additionally, the first heavy tin deposit may serve as an etch resist in subsequent fabrication of the provided circuit board.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 11, 2003
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Arthur J. Demaso, Kathy A. Gosselin, Craig S. Wilson
  • Patent number: 5557843
    Abstract: A printed circuit board and method of manufacture thereof is disclosed. The printed circuit board includes a first substrate provided from a conductive layer having disposed on a first surface thereof a cured adhesive layer, A semi-cured adhesive layer is then disposed over the cured adhesive layer and a second substrate is disposed against the semi-cured adhesive layer.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: September 24, 1996
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Robert D. Cyr
  • Patent number: 5376232
    Abstract: A method of depositing a conductive material on a surface of a printed circuit board, includes the steps of chemically treating at least a portion of a surface of the printed circuit board, disposing a resist layer over the chemically treated surface, depositing a conductive layer in the areas which are not covered by the resist, stripping the resist from the surface of the printed circuit board, and cleaning exposed chemically treated surfaces of the printed circuit board to remove contaminants from the surface of the printed circuit board which were introduced in the chemically treating step.
    Type: Grant
    Filed: August 23, 1993
    Date of Patent: December 27, 1994
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Robert D. Cyr