Patents by Inventor Darsen D. Lu
Darsen D. Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11728428Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.Type: GrantFiled: November 13, 2019Date of Patent: August 15, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
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Patent number: 10903208Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.Type: GrantFiled: January 10, 2020Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
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Patent number: 10892364Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.Type: GrantFiled: November 1, 2017Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
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Patent number: 10886385Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: GrantFiled: April 5, 2019Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Patent number: 10734477Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.Type: GrantFiled: January 11, 2019Date of Patent: August 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
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Publication number: 20200152622Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.Type: ApplicationFiled: January 10, 2020Publication date: May 14, 2020Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
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Patent number: 10593663Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.Type: GrantFiled: August 12, 2016Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
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Publication number: 20200083374Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
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Patent number: 10546955Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.Type: GrantFiled: April 21, 2016Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
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Publication number: 20190237561Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Patent number: 10347752Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: GrantFiled: January 10, 2018Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Publication number: 20190165095Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.Type: ApplicationFiled: January 11, 2019Publication date: May 30, 2019Inventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
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Patent number: 10262991Abstract: The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures.Type: GrantFiled: August 12, 2016Date of Patent: April 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
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Patent number: 10243042Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.Type: GrantFiled: September 7, 2017Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
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Patent number: 10177223Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.Type: GrantFiled: September 7, 2017Date of Patent: January 8, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
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Patent number: 10153157Abstract: A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.Type: GrantFiled: August 26, 2015Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek
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Patent number: 10056474Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: GrantFiled: November 30, 2015Date of Patent: August 21, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Patent number: 9997540Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.Type: GrantFiled: January 17, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Publication number: 20180130894Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: ApplicationFiled: January 10, 2018Publication date: May 10, 2018Inventors: Kangguo CHENG, Bruce B. DORIS, Ali KHAKIFIROOZ, Darsen D. LU, Alexander REZNICEK, Kern RIM
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Patent number: 9966387Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.Type: GrantFiled: November 4, 2016Date of Patent: May 8, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim