Abstract: A vertical stack of semiconductor devices is formed by folding a strip-like flexible interconnector assembled with integrated circuit chips, packages and/or passive components and attaching coupling members solderable to other parts (FIGS. I4A and I4B).

Abstract: A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation.

Abstract: A semiconductor wafer is disclosed comprising a substrate having a surface carrying an array of integrated circuit chips bordered by dicing lines; at least two sets of substantially parallel structures within each of said dicing lines, each set extending along the edge of a chip on opposite sides of each dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively, and a sacrificial composite structure in combination therewith, between said wall and the center of the dicing line, said composite structure including means of dispersing the energy associated with crack propagation, whereby any crack having sufficient energy to penetrate the composite structure will be transformed into a plurality of weaker cracks, non of which will be capable of penetrating said wall.

Abstract: A semiconductor wafer is disclosed comprising a substrate having a surface carrying an array of integrated circuit chips bordered by dicing lines; at least two sets of substantially parallel structures within each of said dicing lines, each set extending along the edge of a chip on opposite sides of each dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively, and a sacrificial composite structure in combination therewith, between said wall and the center of the dicing line, said composite structure including means of dispersing the energy associated with crack propagation, whereby any crack having sufficient energy to penetrate the composite structure will be transformed into a plurality of weaker cracks, non of which will be capable of penetrating said wall.

Abstract: A conductive via pattern (110) between the uppermost metal interconnect layer (Mn ) and next underlying metal interconnect layer (Mn−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).

Abstract: A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: A method for attaching particles (12) to a substrate (14), comprising the steps of transferring adhesive areas (30) from an adhesive stamp (35) to contact pads (42) of the substrate (14), and depositing the particles (12) onto the adhesive areas (30) on the contact pads (42), thereby attaching the particles (12) to the substrate (14). The adhesive stamp (35) may comprise a stamp (20) having at least one projection (22) and an adhesive material applied thereon. The stamp (20) may be composed of silicon, silicone rubber or metal. The adhesive material may be composed of an adhesive polymer or an adhesive flux.

Abstract: An electronic device includes an integrated circuit chip, an interposer and a printed circuit board. A first ball connector is used to connect the interposer to printed circuit board. The interposer may be connected to the integrated circuit chip by a second ball connector or a wire bond. The first ball connector is disposed on a cantilever structure formed in the interposer. The cantilever is formed by creating a channel in the interposer. The cantilever absorbs stress caused by a difference between the thermal expansion of the integrated circuit chip as compared to the printed circuit board. The cantilever thus reduces stress in the ball connector by allowing the ball connector to move within a plane defined by the interposer.

Abstract: A thermal analysis system (10) for analyzing a thermal model of an object is provided which comprises a Gauss-Seidel processor (12) that includes an acceleration factor generator (14). An initial condition generator (16) and a residual energy feedback accelerator (18) are coupled to the Gauss-Seidel processor (12). A data storage (20) is coupled to the Gauss-Seidel processor (12), and a display (22) is coupled to the data storage (20).

Abstract: A system for modeling an integrated chip package and a method of operation is disclosed that includes a parametric processor (1) that provides parameters to define the parts of the package to a volume generator (2). The volume generator (2) uses the parameters to create volumes associated with each part of the integrated chip package. The system (3) provides the volume coordinates to a mesh generator (4). The mesh generator (4) further subdivides the volumes into elements, the elements being small enough for use in finite element analysis. The output of the mesh generator (4) is provided to a finite element analysis processor (5). The finite element analysis processor (5) conducts a physical stress or thermal stress analysis on the package using the elements created by the mesh generator (4). Once the finite element analysis processor (5) has completed its analysis of the package, the result is displayed on a display (6).

Abstract: A base for a multi-chip module that provides for built-in testability. Active test components are embedded in a module substrate. These test components primarily consist of boundary scan cells that comply with the IEEE 1149.1 test standard. The scan cells are connected to each other, and are connected to interconnection paths among chips and to individual chips, thereby partitioning the module into testable partitions. These partitions permit testing of chip interconnections, chip functionality, and module functionality. Scan cell connections may be mask programmable so that the same multi-chip module base can be used for many different multi-chip module configurations.

Abstract: An integrated circuit device is disclosed. In one embodiment, the device has a semiconductor chip having an electrical circuit that is connected to a bonding pad. A metal layer overlies the bonding pad, and a metal bump is connected to the metal layer. The metal bump receives power for the electrical circuit. The method of manufacture allows a designer to form a power supply bus in the metal layer. The metal layer may lie over an active circuit of the semiconductor chip.