Patents by Inventor David A. Albert

David A. Albert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11382554
    Abstract: A personal monitoring device has a sensor assembly configured to sense physiological signals upon contact with a user's skin. The sensor assembly produces electrical signals representing the sensed physiological signals. A converter assembly, integrated with, and electrically connected to the sensor assembly, converts the electrical signals generated by the sensor assembly to a frequency modulated physiological audio signal having a carrier frequency in the range of from about 6 kHz to about 20 kHz.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 12, 2022
    Assignee: AliveCor, Inc.
    Inventors: David Albert, Bruce Richard Satchwell, Kim Norman Barnett
  • Publication number: 20220199251
    Abstract: Described herein are software platforms (or “platforms”), systems, devices, and methods for providing effective healthcare to a patient while increasing the efficiency of the healthcare provider. A platform provides effective healthcare to a patient through, but not limited to, monitoring of the physical parameters and therapeutic objectives of the patient. In addition, a platform is further configured to provide a communication link between a patient and a healthcare provider. The platform may be implemented by a system comprising one or more computing devices that interact with or run one or more applications of the platform.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Frank Petterson, Melissa McLean, Arthur Okamoto, James Jenkins, Vivek Gundotra, David Albert
  • Patent number: 11357972
    Abstract: Methods and systems for alleviating disorders and complications associated with autonomic nervous system dysfunction. The approach generally includes measuring heart rate signals from a subject to measure heart rate variability and determine a heart rate variability threshold, determining that the subject is experiencing autonomic nervous system dysfunction, and alerting the subject to stimulate the auricular branch of the vagus nerve with an ear device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 14, 2022
    Assignee: The Board of Regents of the University of Oklahoma
    Inventors: Sunny Po, Benjamin Scherlag, Stavros Stavrakis, Paul Garabelli, David Albert
  • Publication number: 20220146535
    Abstract: The present invention provides compounds and methods targeting human tau, particularly human tau phosphorylated at threonine 217 and isoforms of tau expressed only in the CNS, including therapeutic antibodies, pharmaceutical compositions and diagnostic applications useful in the field of neurodegenerative diseases such as AD, PSP and FTD.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 12, 2022
    Inventors: Xiyun CHAI, Jinbiao CHEN, Jeffrey L. Dage, David Albert Driver, Steven Fisher Hinton, Robert William Siegel, II, Peter Edward Vaillancourt
  • Patent number: 11327759
    Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 10, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: David Albert Carlson, Shubhendu Sekhar Mukherjee, Michael Bertone, David Asher, Daniel Dever, Bradley D. Dobbie, Thomas Hummel
  • Patent number: 11276491
    Abstract: Software applications, devices, systems, and methods are provided for monitoring, recording, and tracking cardiac health related metrics using an associated computing device. The software applications may monitor, record, and track physiological data such as cardiac electrical activity, heart rate, and blood pressure. Data transmission between a patient and a healthcare provider may also be enabled via the software applications disclosed herein.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 15, 2022
    Assignee: AliveCor, Inc.
    Inventors: Frank Petterson, Melissa McLean, Arthur Okamoto, James Jenkins, Vivek Gundotra, David Albert
  • Patent number: 11254039
    Abstract: An injection molding machine includes an edge gate nozzle with a nozzle body having a primary melt channel and a nozzle head having first and second secondary melt channels that feed melt to first and second nozzle tips. First and second heaters are disposed in the nozzle head to provide heat to the secondary melt channels. In some embodiments, the heaters are positioned adjacent to the secondary melt channels, with first heater is closer to the first secondary melt channel than to the second secondary melt channel. In some embodiments, the heaters are positioned adjacent to the nozzle tips, with the first heater closer to the first nozzle tip than to the second nozzle tip. In some embodiments, each heater is adjacent to both the respective nozzle tip and secondary melt channel. In some embodiments, each heater is individually controllable.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 22, 2022
    Assignee: HUSKY INJECTION MOLDING SYSTEMS LTD.
    Inventors: Sarah Kathleen Overfield, Edward Joseph Jenko, Brian Esser, David Albert Hurley
  • Publication number: 20210374777
    Abstract: An instrument for measuring and presenting customer impressions of a vendor uses response values of survey questions to develop a consumer loyalty score, vendor attribute score, and/or a consumer experience score. The scores may be presented with other score sets for other vendors to provide a simple and consistent comparison of vendors. Vendor characteristics and/or categories are modeled to more accurately reflect the importance of specified characteristics and/or categories that affect consumer loyalty.
    Type: Application
    Filed: February 5, 2016
    Publication date: December 2, 2021
    Inventors: Michael James Schwerin, David Albert Ritter, Samuel Carl Karpen, Jeffrey Allen Smith, Joshua Thomas Rohlfs, Andrew Lee Salmonson
  • Patent number: 11176055
    Abstract: A pipeline in a processor core includes: at least one stage that decodes instructions including load instructions that retrieve data stored at respective virtual addresses, at least one stage that issues at least some decoded load instructions out-of-order, and at least one stage that initiates at least one prefetch operation. Copies of page table entries mapping virtual addresses to physical addresses are stored in a TLB. Managing misses in the TLB includes: handling a load instruction issued out-of-order using a hardware page table walker, after a miss in the TLB, handling a prefetch operation using the hardware page table walker, after a miss in the TLB, and handling any software-calling faults triggered by out-of-order load instructions handled by the hardware page table walker differently from any software-calling faults triggered by prefetch operations handled by the hardware page table walker.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Publication number: 20210011729
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Patent number: 10886888
    Abstract: A bulk acoustic wave (BAW) resonator is disclosed. The BAW resonator includes: a lower electrode; a piezoelectric layer disposed over the lower electrode; and an upper electrode over the piezoelectric layer. An opening having a first area exists in and extends completely through the upper electrode. The BAW resonator also includes a substrate disposed below the lower electrode; a cavity; and a pillar disposed in the cavity and extending to contact a portion of the lower electrode disposed beneath the opening. The pillar has a second area that is less than the first area. There are no electrical connections that extend across the opening from one side to another.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 5, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Brice Ivira, Chris Kirkendall, Pen Li Yu, Sormeh Setoodeh, David Albert Feld
  • Publication number: 20200379772
    Abstract: A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
  • Patent number: 10817300
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 27, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Publication number: 20200324105
    Abstract: Methods and systems for alleviating disorders and complications associated with autonomic nervous system dysfunction are provided. The approach generally includes measuring heart rate signals from a subject to measure heart rate variability and determine a heart rate variability threshold, determining that the subject is experiencing autonomic nervous system dysfunction, and alerting the subject to stimulate the auricular branch of the vagus nerve with an ear device.
    Type: Application
    Filed: December 14, 2018
    Publication date: October 15, 2020
    Inventors: Sunny Po, Benjamin Scherlag, Stavros Stavrakis, Paul Garabelli, David Albert
  • Publication number: 20200273567
    Abstract: Software applications, devices, systems, and methods are provided for monitoring, recording, and tracking cardiac health related metrics using an associated computing device. The software applications may monitor, record, and track physiological data such as cardiac electrical activity, heart rate, and blood pressure. Data transmission between a patient and a healthcare provider may also be enabled via the software applications disclosed herein.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Frank Petterson, Melissa McLean, Arthur Okamoto, James Jenkins, Vivek Gundotra, David Albert
  • Patent number: 10747543
    Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
  • Publication number: 20200210195
    Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
  • Patent number: 10685090
    Abstract: Software applications, devices, systems, and methods are provided for monitoring, recording, and tracking cardiac health related metrics using an associated computing device. The software applications may monitor, record, and track physiological data such as cardiac electrical activity, heart rate, and blood pressure. Data transmission between a patient and a healthcare provider may also be enabled via the software applications disclosed herein.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 16, 2020
    Assignee: AliveCor, Inc.
    Inventors: Frank Petterson, Melissa McLean, Arthur Okamoto, James Jenkins, Vivek Gundotra, David Albert
  • Patent number: 10664611
    Abstract: A broadband gateway, which enables communication with a plurality of devices, handles at least one physical layer connection to at least one corresponding network access service provider. The broadband gateway may operate as a home gateway to negotiate with one or more visited gateways, a common authorized service area or domain (ASD) for providing services to the visited gateways. The home gateway may establish one or more corresponding communication links with the visited gateways based on the negotiated common ASD. The home gateway communicates corresponding content for the services to the visited gateways via the established corresponding communication links. The home gateway communicates information about gateway functionalities required for the services to the visited gateways.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Xuemin Chen, Jeyhan Karaoguz, Wael William Diab, David Garrett, David Albert Lundgren, Rich Prodan
  • Publication number: 20200133680
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone