Abstract: A system for measurement is provided. The system includes a first optical path configured to supply first light pulses with a first range of wavelengths; a second optical path configured to supply second light pulses with a second range of wavelengths shorter than the first range of wavelengths; an optical I/O unit configured to emit the first light pulses and the second light pulses to a target and acquire a light from the target to detect CARS light pluses from the target by a detector; and a first phase modulating unit configured to vary phase differences between the first light pulses and the second light pulses as the first light pulses and the second light pulses are emitted via the optical I/O unit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

Abstract: Devices, systems, and methods for evaluating a vessel of a patient are provided. The method includes outputting, to a touch-sensitive display of a bedside controller, a screen display including: a visual representation of a first pressure ratio of pressure measurements obtained by first and second instruments positioned within a vessel while the second instrument is moved from a distal position to a proximal position relative a stenosis and the first instrument remains stationary; and a first proximal pressure waveform and a first distal pressure waveform; receiving, through the touch-sensitive display of the bedside controller, a user touch input on the first proximal pressure waveform and/or the first distal pressure waveform identifying a time at which pressure measurements were obtained; and modifying the screen display, in response to the user touch input, to further include a visual representation of the obtained pressure measurements corresponding to the identified time.

Abstract: Systems and method for automated self-testing of a protective device for a transformer are disclosed. One system includes a protection circuit electrically connected to a transformer neutral, the transformer electrically connected to a power grid, the protection circuit may include a DC blocking component, a switch assembly, and a spark gap assembly each positioned in parallel between the transformer neutral and ground, a switch assembly. The system may further include various testing circuits configured within the protection circuit and switches which when actuated inject a signal to test various components in the protective device.

Abstract: A circuit includes a detector and controller circuit configured to detect a high field RF (radio frequency) electromagnetic fields indicating a potential of an electromagnetic pulse event capable of damaging electrical equipment connected to a power grid. The circuit also includes controller receiving an input from the detector circuit, the controller being included within a shielded enclosure and configured to initiate an event in response to detection of the high field electromagnetic pulse field to remove the electrical equipment from the power grid.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

Abstract: Golf club heads include white diffusing top surfaces to aid in club head alignment. Wood type club heads also include a dark diffusing club face so that a crown/face border is emphasized. Scorelines in wood type clubs can be provided with an intermediate contrast surface, and can be displaced from club face center to accommodate player perception when confronted with a white diffusing crown. Putter heads can include dark diffusing alignment lines, and iron-type club heads can include white diffusing surfaces at a sole portion of a club face, at a top line, or a top portion of a club face.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Abstract: An aqueous based drilling fluid that exhibits improved lubricity, containing a phospholipid lubricant component and methods of improving the lubricity of an aqueous based drilling fluids. The methods include improving the lubricity of an aqueous based drilling fluid composed of an aqueous base fluid, and a weighting agent, with the addition of an effective amount of a phospholipid to substantially reduce the coefficient of friction when compared to the fluid absent the phospholipids.

Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Abstract: Disclosed herein are systems, methods, and devices for sensing touch at a surface. Sensing touch can be achieved while decreasing the number of sensors at a surface as well as data and computation complexity, but maintaining accuracy. Such sensing touch can be achieved via applying excitation and detecting emission waveforms at a surface that are associated with touch at a surface.

Abstract: A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.

Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.