Abstract: A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

Abstract: A device, such as Network Microphone Device or a playback device, receives an indication of a track change associated with a playback queue output by a media playback system. In response, an input detection window is opened for a given time period. During the given time period the device is arranged to receive an input sound data stream representing sound detected by a microphone. The input sound data stream is analyzed for a plurality of command keywords and/or a wake-word for a Voice Assistant Service (VAS) and, based on the analysis, it is determined that the input sound data stream includes voice input data comprising a command keyword or a wake-word for a VAS. In response, the device takes appropriate action such as causing the media playback system to perform a command corresponding to the command keyword or sending at least part of the input sound data stream to the VAS.

Abstract: A method for atom-based closed-loop control includes exciting atoms of a gas into one or more Rydberg states, applying one or more signal processing functions to the one or more Rydberg states, and regulating a characteristic of the applied one or more signal processing functions based on, at least in part, a response of the one or more Rydberg states to the one or more signal processing functions. A system for internal quantum-state-space interferometry includes an atomic receiver, an interferometric pathway, and a detector. The interferometer includes an atomic vapor with first atomic states and second atomic states. The interferometric pathway from RF phases between the first and second atomic states is closed by a quantum-state-space. The detector is configured to detect a readout of an interferometric signal. Embodiments include atom-based automatic level control, baseband processors, phase-locked loops, voltage transducers, raster RF imagers and waveform analyzers.

Abstract: The present invention relates to methods, kits and a test strip for detecting gut barrier dysfunction and/or cirrhosis in a subject. In addition, a method of treating a subject with gut barrier dysfunction and/or cirrhosis is provided.

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

Abstract: The present embodiments provide systems and methods for aggregating measurements captured by different technologies during a golf swing. By capturing measurements using different technologies, more accurate measurements may be provided to a user by selecting from the measurements, offsetting measurements based on the technologies used, and aligning measurements between devices. Further, by aggregating measurements received from different devices, additional features and functionality may be provided to the user that is absent from any one device used alone. Additionally, by storing the aggregated measurements, users, club fitters and instructors may access and leverage larger databases of measurements to better understand the user's golf swing and to provide better recommendations and instruction to the user.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

Abstract: An air separation module includes a canister extending between a first end and an opposite second end, a separator fixed within the canister to separate a compressed air flow into an oxygen-enriched air flow fraction and an oxygen-depleted air flow fraction, and a one-piece cap. The one-piece cap is connected to the first end of the canister and has a filter module mount portion on a side of the one-piece cap opposite the separator to support a filter module with the air separation module. Nitrogen generation systems and methods of making air separation modules are also described.

Abstract: Embodiments of a system as described herein may receive financial institution product information from a plurality of financial institutions distributed across a computing network. The system may also receive data from the plurality of financial institutions distributed across the computer network and create or update an ontology. A relevance score may be generated for a set of financial institution products which may, in conjunction with a campaign definition provided by a financial institution administrator, be used to associate users with a list of campaigns which may be stored as campaign data. An online banking application at a user device may request campaign data for a user. In response, the system may return campaign data for the user to the online banking application. Using the campaign data, the online banking application may select one or more products to recommend to the user and display content for the selected products on the user device.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: Devices, systems, and methods for evaluating a vessel of a patient are provided. The method includes outputting, to a touch-sensitive display of a bedside controller, a screen display including: a visual representation of a first pressure ratio of pressure measurements obtained by first and second instruments positioned within a vessel while the second instrument is moved from a distal position to a proximal position relative a stenosis and the first instrument remains stationary; and a first proximal pressure waveform and a first distal pressure waveform; receiving, through the touch-sensitive display of the bedside controller, a user touch input on the first proximal pressure waveform and/or the first distal pressure waveform identifying a time at which pressure measurements were obtained; and modifying the screen display, in response to the user touch input, to further include a visual representation of the obtained pressure measurements corresponding to the identified time.

Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

Abstract: Described herein are systems, methods, and software to manage private networks for computing elements. In one example, a computing element on a first local network communicates a request to a coordination service to join a private network. The computing element further receives communication information associated with other computing elements in the private network, wherein the communication information permits the computing element to communicate with other computing elements in the private network that connect to the internet using second local networks. The computing element further advertises the computing elements in the first local network as though the other computing elements are connected to the first local network.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.