Patents by Inventor David A. Baglee
David A. Baglee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5681768Abstract: A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14) insulates a gate conductor (16) from the channel region (34). A sidewall insulator body (20) is formed such that a thickened region of insulator separates an end of gate conductor (16) from a portion of channel region (34) proximate drain region (24). This thickened insulator reduces the local electric field in channel region (34) near drain region (24) and correspondingly reduces the implantation into gate insulator (14) of hot carriers generated from impact ionization.Type: GrantFiled: June 7, 1995Date of Patent: October 28, 1997Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, David A. Baglee
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Patent number: 5679968Abstract: A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14) insulates a gate conductor (16) from the channel region (34). A sidewall insulator body (20) is formed such that a thickened region of insulator separates an end of gate conductor (16) from a portion of channel region (34) proximate drain region (24). This thickened insulator reduces the local electric field in channel region (34) near drain region (24) and correspondingly reduces the implantation into gate insulator (14) of hot carriers generated from impact ionization.Type: GrantFiled: January 31, 1990Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, David A. Baglee
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Patent number: 5374580Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.Type: GrantFiled: September 30, 1993Date of Patent: December 20, 1994Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Robert R. Doering, Gregory J. Armstrong
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Patent number: 5170234Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.Type: GrantFiled: August 27, 1991Date of Patent: December 8, 1992Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Robert R. Doering, Gregory J. Armstrong
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Patent number: 5049958Abstract: A dynamic read/write memory cell array employs stacked capacitors consisting of three levels of conductor separated by dielectric material. In one embodiment, the central level is a common plane, and the upper and lower levels are connected to the source regions of the pair of access transistors of two adjacent cells. In this manner, capacitors for adjacent cells occupy the same area, almost doubling the capacitor value per unit area.Type: GrantFiled: May 8, 1990Date of Patent: September 17, 1991Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4975383Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.Type: GrantFiled: March 15, 1990Date of Patent: December 4, 1990Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4975384Abstract: An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.Type: GrantFiled: July 11, 1988Date of Patent: December 4, 1990Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4928267Abstract: A method of reconditioning an electrically programmable semiconductor read only memory cell which includes heating the cell to a temperature which is sufficiently high and for a sufficient duration so that the Write/Erase window is re-opened.Type: GrantFiled: September 16, 1985Date of Patent: May 22, 1990Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Ronald N. Parker
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Patent number: 4891747Abstract: A dynamic RAM cell of the contactless type with a buried N+ source/drain region is constructed by the metal-gate non-self-aligned technique. A lightly-doped drain is provided by employing both arsenic and phosphorus in the buried N+ region. The effects of impact ionization are thus minimized, and a high density cell array is provided.Type: GrantFiled: August 22, 1986Date of Patent: January 2, 1990Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4835741Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.Type: GrantFiled: June 2, 1986Date of Patent: May 30, 1989Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4830981Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.Type: GrantFiled: January 25, 1988Date of Patent: May 16, 1989Assignee: Texas Instruments Inc.Inventors: David A. Baglee, Ronald Parker
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Patent number: 4796228Abstract: An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.Type: GrantFiled: June 2, 1986Date of Patent: January 3, 1989Assignee: Texas Instruments IncorporatedInventor: David A. Baglee
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Patent number: 4721987Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.Type: GrantFiled: July 3, 1984Date of Patent: January 26, 1988Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Ronald Parker
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Patent number: 4718041Abstract: Disclosed is a method and apparatus for extending the programmable life of an EEPROM memory. For each write commamd generated external to the memory an automatic internal read operation is executed. Each internally generated read operation is accompanied by an increased sense voltage. Data written into selected cells is temporarily stored and compared with the data read. If a match of the compared data is found, the memory operations continue as usual. If a mismatch is found, an internally generated write operation is generated, the programming voltage is increased, and the data temporarily stored is rewritten at the increased voltage. Data polling features are provided with both the internal and externally generated write operations.Type: GrantFiled: January 9, 1986Date of Patent: January 5, 1988Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Michael C. Smayling
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Patent number: 4641173Abstract: One embodiment of the present invention provides a polycrystalline silicon loading device occupying a minimum of surface area in an integrated circuit. A very thin layer of silicon nitride is formed on the surface of a heavily doped contact point in the integrated circuit. An undoped layer of polycrystalline silicon is then formed on the surface of this thin layer of silicon nitride. A thin layer of silicon nitride is then formed on the surface of the undoped polycrystalline silicon layer. Finally a heavily doped polycrystalline silicon layer for making contact to the loading device is formed on the surface of the second thin silicon nitride layer. Because the two thin silicon nitride layers are very thin, tunneling current through the silicon nitride layers begins at a fairly low threshold level. After tunneling occurs, the main resistance element of the load device is the undoped polycrystalline silicon.Type: GrantFiled: November 20, 1985Date of Patent: February 3, 1987Assignee: Texas Instruments IncorporatedInventors: Satwinder Malhi, David A. Baglee
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Patent number: 4569117Abstract: A method of making MOS integrated circuits employs high-pressure oxidation of the surface of a silicon slice to create thermal field oxide for device isolation. The implant used prior to this oxidation to provide the channel-stop regions beneath the field oxide may be at a lower dosage, and yet the field-transistor threshold voltage is maintained at a high level. Thus, encroachment of the channel stop impurity into the transistor channel is minimized, and higher density devices are permitted.Type: GrantFiled: May 9, 1984Date of Patent: February 11, 1986Assignee: Texas Instruments IncorporatedInventors: David A. Baglee, Michael C. Smayling, Michael P. Duane, Mamoru Itoh
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Patent number: RE33261Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.Type: GrantFiled: March 2, 1989Date of Patent: July 10, 1990Assignee: Texas Instruments, IncorporatedInventors: David A. Baglee, Ronald Parker