Abstract: A high-density laminated connector having a plurality of rigid dielectric layers laminated together is described. The rigid construction of the connector permits precise dimensions of the connector and, thus, accurate attachment of adjacent interconnect substrates. The dielectric layers include traces which have contact pads or bumps formed at the surfaces of the connector for connection to the traces of one or more adjacent interconnect substrates. The contact pads may comprise soft gold, solder, or various elastomeric materials. The use of soft gold contacts enables the connector to be easily removed from an adjacent interconnect substrate. In other embodiments, the rigid dielectric layers may comprise recesses where the contact pads are placed. This ensures physical alignment of the interconnect substrate and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction.

Abstract: A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included.

Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.

Abstract: A high-density laminated connector comprises a plurality of layers of rigid dielectric material which are laminated together. The rigid construction of the connector permits precise dimensions of the connecter and, thus, accurate attachment of adjacent circuit boards. The dielectric contains traces which are joined to contact pads, connecting the traces to adjacent circuit boards. The contact pads are comprised of soft gold, solder, and various elastomeric materials. The use of soft gold contacts allows the connector to be easily removed from the adjacent circuit board. Alternatively, the rigid dielectric layers contain recesses where the contact pads are placed. This ensures physical alignment of the circuit board and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction. Thus, right-angle interconnections can be made.

Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.