Abstract: A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.

Abstract: An error recovery method for use in an information communication system which comprises a plurality of nodes connected by links. Information is transferred between the nodes in frames of predefined types, including at least a first frame type used to transfer data and a second frame type used for error recovery. Each node has at least a first and a second mode of operation. In the first mode frames of both first and second types are accepted. In the second mode frames of the first type are discarded and only frames of the second type are accepted. A master node which controls error recovery is selected from amongst those nodes which can initiate transfers.

Abstract: Described is a system and method of communicating between first and second nodes connected by a serial link wherein the data is transmitted between the nodes in the form of packets made up of multiple bit frames. Each packet that is correctly received by the second node is acknowledged by means of a pair of multibit frames. These frames may be interleaved among the frames making up any outgoing data packet that is being transmitted by the second node. The technique employed provides unambiguous acknowledgment of each data packet and if a data packet is received incorrectly, the packet is available in a buffer in the first node for resending.

Abstract: Disclosed is an array controller for controlling the transfer of data from a host system to an array of data storage devices, comprising a processor connected via a local bus to a data buffer in which data is staged during said transfer. The array controller is provided with a buffer controller for controlling the operation of the buffer and is further provided with channel hardware for manifesting a plurality of data channels, selectable by the local bus address, over which data is transferred in and out of the data buffer.

Abstract: A system is provided for storing data for a plurality of host computers on a plurality of storage arrays so that data on each storage array can be accessed by any host computer. A plurality of adapter cards are used. Each adapter has controller functions for a designated storage array. There is an adapter communication interface (interconnect) between all of the adapters in the system. There is also a host application interface between an application program running in the host computer and an adapter. When a data request is made by an application program to a first adapter through a host application interface for data that is stored in a storage array not primarily controlled by the first adapter, the data request is communicated through the adapter communication interface to the adapter primarily controlling the storage array in which the requested data is stored.