Abstract: A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided for improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure comprises a processor. The processor comprises a cache, an execution unit, and circuitry. The circuitry is configured to receive a branch instruction from the cache to be executed in a program order. The circuitry is further configured to, before execution of the branch instruction in the program order, issue the branch instruction to the execution unit to determine a predicted outcome of the branch instruction, and use the predicted outcome of the branch instruction to schedule execution of one or more instructions succeeding the branch instruction in the program order.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally comprises a processor, which generally comprises a cache, a dual instruction queue comprising a first queue and a second queue, an execution unit, and circuitry. The circuitry is configured to receive branch instructions, issue instructions for the branch instruction's first path to the first queue, issue instructions for the branch instruction's second path to the second queue, and determine if the branch instruction follows the first or second path. The control circuitry is further configured to, upon determining that the branch instruction follows the first path, provide the instructions for the first path from the first queue to the execution unit, and upon determining that the branch instruction follows the second path, provide the instructions for the second path from the second queue to the execution unit.

Abstract: A design structure for prefetching instruction lines is provided. The design structure is embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design. The design structure comprises a processor. The processor generally comprises a level 2 cache, a level 1 cache configured to receive instruction lines from the level 2 cache, wherein each instruction line comprises one or more instructions, a processor core configured to execute instructions retrieved from the level 1 cache; and circuitry. The circuitry is configured to fetch a first instruction line from a level 2 cache, identify, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line, extract an address from the identified branch instruction; and prefetch, from the level 2 cache, a second instruction line containing the targeted instruction using the extracted address.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for minimizing unscheduled D-cache miss pipeline stalls is provided. The design structure includes an integrated circuit device, which includes a cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other, and circuitry. The circuitry is configured to receive an issue group of instructions, determine whether the issue group is a load instruction, and if so, schedule the load instruction in a first pipeline of the two or more execution pipelines, and schedule each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the first pipeline begins prior to beginning execution of the remaining instructions in the remaining pipelines.

Abstract: A design structure for prefetching instruction lines is provided. The design structure is embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design. The design structure comprises a processor having a level 2 cache, and a level 1 cache configured to receive instruction lines from the level 2 cache is described, wherein each instruction line comprises one or more instructions. The processor also includes a processor core configured to execute instructions retrieved from the level 1 cache, and circuitry configured to fetch a first instruction line from a level 2 cache, identify, in the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line, and prefetch, from the level 2 cache, the first data line using the extracted address.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, an L2 cache may be operated in a store-through mode, whereby data from store instructions that cause L1 misses are sent directly to the L2 cache without causing pipeline stalls. The store-through mode may be enabled or disabled (e.g., under software and/or hardware control). Higher levels of cache (e.g., L3 and L4) may also be operated in a store-through mode.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.

Abstract: A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the primary latch, then transferred to the secondary latch. The bit value for a first thread of execution is then written to the primary latch. When a context switch is needed (when the first thread stalls and the second thread needs to begin execution), the register file bit can perform a context switch from the first thread to the second thread in a single clock cycle. The register file bit contains a backup latch inside the register file itself so that minimal extra wire paths are needed to or from the existing register file.

Abstract: An apparatus and method is described for improving access to mostly read data on network servers. The preferred embodiments more efficiently utilize replicated data servers to minimize server response time for improved performance of data access to network servers by workload managing client requests across the primary server and all replicated servers when it is possible to do so. In preferred embodiments, a load balancer supplies the most current data for mostly read data transactions while maximizing server usage by workload managing client requests across the primary server and all replicated servers. Client requests are managed by a load balancer in the workload manager. Client requests are sent by the load balancer to replicated servers when a routing table (stale data marker list) indicates that the data is in a safe period. Clients are directed exclusively to the primary server only during data update times.

Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction and issuing one or more instructions from a first path of the branch instruction and one or more instructions from a second path of the branch instruction. If the first path of the branch instruction is followed by the branch instruction, the one or more instructions from the second path of the branch instruction are invalidated. If the second path of the branch instruction is followed by the branch instruction, the one or more instructions from the first path of the branch instruction are invalidated.

Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction. The method further includes issuing the one or more interceding instructions and the target instruction and determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the one or more interceding instructions between the branch instruction and the target instruction are invalidated.

Abstract: Embodiments of the invention provide a method and processor for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction to be executed in the processor and detecting a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The method further includes scheduling execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.