Abstract: Embodiments of the invention provide a method and apparatus of storing branch prediction information. In one embodiment, the method includes receiving a branch instruction and storing local branch prediction information for the branch instruction including a local predictability value for the local branch prediction information. The method further includes storing global branch prediction information for the branch instruction only if the local predictability value is below a threshold value of predictability.

Abstract: Embodiments provide a method and apparatus for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction and calculating a load effective address of load data for the load instruction and a store effective address of store data for the store instruction. The method further includes comparing the load effective address with the store effective address and speculatively forwarding the store data for the store instruction from a first pipeline in which the store instruction is being executed to a second pipeline in which the load instruction is being executed. The load instruction receives the store data from the first pipeline and requested data from a data cache. If the load effective address matches the store effective address, the speculatively forwarded store data is merged with the load data. If the load effective address does not match the store effective address the requested data from the data cache is merged with the load data.

Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, issuing instructions for a first path of the branch instruction to a first queue of a dual instruction queue, and issuing instructions for a second path of the branch instruction to a second queue of a dual instruction queue. The method further includes determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the instructions for the first path are provided from the first queue are provided to a first execution unit. Upon determining that the branch instruction follows the second path, instructions for the second path are provided from the second queue to the first execution unit.

Abstract: A method and apparatus for executing a branch instruction is provided. In one embodiment, the method includes determining if a predictability value for the branch instruction is below a threshold value. Upon determining that the predictability value is above or equal to the threshold value, branch prediction information for the branch instruction is used to predict the outcome of the branch instruction. Upon determining that the predictability value for the branch instruction is below the threshold value for predictability, an alternate method of executing the branch instruction is selected. The alternate method comprises at least one of preresolving the branch instruction, simultaneously issuing first instructions from a first path of the branch instruction and second instructions from a second path of the branch instruction, and buffering the first instructions from the first path of the branch instruction and the second instructions from the second path of the branch instruction.

Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, In one embodiment, the method includes receiving the branch instruction to be executed in a program order and, before execution of the branch instruction in the program order, issuing the branch instruction to an execution unit to determine a predicted outcome of the branch instruction. The method further includes using the predicted outcome of the branch instruction to schedule execution of one or more instructions succeeding the branch instruction in the program order.

Abstract: An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.

Abstract: A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of the consecutive number of outstanding instructions. By being able to track a consecutive number of outstanding instructions, such as the length of a cache line, in each entry in the completion table by only storing the instruction address and identification of the first of the consecutive number of outstanding instruction in that entry, the completion table may be able to track a larger number of outstanding instruction without increasing its size.

Abstract: A self repairable processor that provides a reliable computing result without increasing the footprint of the on-chip devices. The processor has a plurality of data registers connected to two identical functional units, where only one of the functional units is enabled for computing, the two functional units being placed in a chip area defined at most by data paths needed for one functional unit. When an error condition is detected in the active functional unit, the processor disables the functional unit with an error condition and enables the duplicate functional unit.

Abstract: Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, extracting, from the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line; and prefetching, from the level 2 cache, the first data line using the extracted address.

Abstract: A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

Abstract: A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

Abstract: Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, identifying, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line, extracting an address from the identified branch instruction, and prefetching, from the level 2 cache, a second instruction line containing the targeted instruction using the extracted address.

Abstract: A computer system having data registers for storing uncompressed data, a data queue for storing data to be compressed, a compressor for compressing data in the data queue, and a compression ratio monitor for determining the compression ratio of the compressed data. The computer system also includes a compression control register that holds control information, and a precision reducer for reducing the precision of the data prior to that data being stored in the data queue. The precision reducer responses to control information to reduce the precision of the data such that the resulting reduced precision data can be more efficiently compressed. The control information, and thus the operation of the precision reducer, depends on the compression ratio monitor.

Abstract: Compressed memory systems and methods that reduce problems of memory overflow and data loss. A compression engine compresses blocks of data for storage in a compressed memory. A compression monitor monitors the achieved compression ratio and provides a software trap when the achieved compression ratio falls below a minimum. After the trap is provided software monitors the fill state of the compressed memory. If the compressed memory is approaching full, the software changes the block size to improve the compression ratio.

Abstract: Methods and systems for managing power and energy expenditures in cores of a processor to balance performance with power and energy dissipation are disclosed. Embodiments may include pre-decoder(s) between levels of cache or between main memory and a level of cache to monitor core execution rates by associating power tokens with each instruction. The power tokens include values representing the average power dissipated by the core for instructions and a sum of the power tokens may be compared with a state of management control bits for performance, energy, and power, to determine whether to increase or decrease power dissipation in the core. The power dissipation is varied by, e.g., adjusting the issue rate of instructions, adjusting the execution rate of instructions, turning off unused units within the core, controlling the frequency and voltage of the core, and switching tasks between cores.

Abstract: A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in an array. A pipeline failure causes data to be shifted one position within the array of pipelines, to by-pass the failing pipeline, so that each pipeline has only two sources of data, a primary and an alternate. Preferably, selection logic controlling the selection between a primary and alternate source of pipeline data is integrated with other pipeline operand selection logic.

Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.

Abstract: A system and method for reducing the power consumption in a floating point unit of a processor executing an iterative loop of a program by inhibiting floating point register file writes of interim values of the loop from the floating point multiply adder (FPMADD) unit. A plurality of pipeline registers is resident on the processor and holds a portion of an unrolled loop, and once the end of the loop is detected, the last value produced from the loop in the FPMADD unit is written to the floating point registers.

Abstract: Methods and systems for repairing ports are disclosed. Embodiments may detect a hard failure of a port, select an alternative port from existing ports in use within an array, and share the alternative port to route operands bound for the first port and the alternative port, to transmit operands associated with the failed port to the corresponding destination unit. Embodiments include an additional wire, or an alternative port path, that couples the alternative port to the destination unit that is associated with the first port. For instance, in a multi-pipeline processor, an operand of an instruction that is bound for the failed read port may be routed via an alternative read port to the corresponding execution unit. Similarly, data bound for failed write ports may be, e.g., written back to a register file by routing the data via an alternative write port of the register file.

Abstract: An instruction, corresponding methods, and circuitry for efficiently performing partial dot sum products are provided. The instruction may include a source select field for specifying one or more source word elements to participate in the dot sum operation. The instruction may also include a target select field for specifying one or more (or none) target word elements for storing the result of the dot sum operation.