Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: Systems and techniques for modifying a subsection of uploaded media are presented. An instruction component receives a media file and a media enhancement instruction that includes enhancement data and media interval data for a first segment of the media file. A processing component modifies the first segment of the media file associated with the media interval data based on the enhancement data to generate an edited first segment of the media file. A finalization component generates an edited version of the media file that includes the edited first segment of the media file and at least a second segment of the media file that is not modified based on the enhancement data.

Abstract: The invention provides antibodies and antigen-binding fragments thereof that selectively bind to an epitope within the core region of transglutaminase type 2 (TG2). Novel epitopes within the TG2 core are provided. The invention provides human TG2 inhibitory antibodies and uses thereof, particularly in medicine, for example in the treatment and/or diagnosis of conditions including Celiac disease, scarring, fibrosis-related diseases, neurodegenerative/neurological diseases and cancer.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

Abstract: Exemplary embodiments of a kamado-style cooker pizza oven conversion device are disclosed. Certain embodiments detachably mount within a kamado-styled cooker such that the lid of the cooker rests at an angle on the top of the device and thereby “closes off” and defines a cooking space within the interior that takes advantage of the pizza oven-like features of a kamado cooker. With an embodiment of the solution installed in a kamado cooker, an open doorway or window is defined for allowing a user to insert a pizza into the cooking space and place the pizza on a pizza stone held by the device. Embodiments allow for cooking to occur simultaneously via conductive, convective and radiant thermal energy transfer.

Abstract: A method for representing a second presentation of audio channels or objects as a data stream, the method comprising the steps of: (a) providing a set of base signals, the base signals representing a first presentation of the audio channels or objects; (b) providing a set of transformation parameters, the transformation parameters intended to transform the first presentation into the second presentation; the transformation parameters further being specified for at least two frequency bands and including a set of multi-tap convolution matrix parameters for at least one of the frequency bands.

Abstract: The present invention relates to humanised antibodies that bind amyloid peptides, which antibodies comprise mutations in the heavy chain and/or light chain variable domains, which mutations improve the binding activity. The antibodies may be useful in the treatment of Alzheimer's disease (AD).

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

Abstract: A printing plate pressure adjustment system for a can decorator including a printing plate cylinder assembly having a printing plate cylinder drive shaft, and a blanket wheel. The system includes an actuator, a control system structured to control operation of the actuator to adjust a pressure between the printing plate cylinder assembly and the blanket wheel, an eccentric bushing disposed around the printing plate cylinder drive shaft, wherein rotation of the eccentric bushing causes the printing plate cylinder to move toward or away from the blanket wheel, and a drive mechanism coupled between the actuator and the eccentric bushing, wherein operation of the actuator causes the drive mechanism to rotate the eccentric bushing.

Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: A railway tie, and method for producing said railway tie, includes an outer shell having an inner surface defining a shell void in the outer shell. A void material fills the shell void. An insert is located in the shell void and spans from a first side of the outer shell to a second side of the outer shell and reinforces the outer shell against force applied to one or both of the first side and the second side. The insert may include an insert-shell component, and a conduit component located in the insert-shell component, the conduit component sized and shaped to receive a railway fastener.