Abstract: Embodiments of an interconnect apparatus advantageously useful in handling Big Data Graph Analytics enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array.

Abstract: Dispenser systems, dispensers, and repositories can add a fragrance to an unscented liquid beauty preparation. The dispenser system includes a dispenser having a cavity for retaining at least a first liquid, and a repository configured for removably attaching to the dispenser, the repository having a reservoir for retaining at least a second liquid. The dispenser is coupled with a pump assembly including at least one pump for drawing the at least a first liquid and the at least a second liquid into a mixing chamber. The mixing chamber is coupled with an actuator in such a manner that when the actuator is pressed down by an external force, the mixing chamber communicates with the pump to suction the first and second liquids into the mixing chamber to form a liquid mixture for dispensing through a nozzle.

Abstract: Techniques are disclosed for auditing an IP address prefix that has been assigned to an entity as part of an administrator policy, to determine whether the assignment was implemented on the network. In an embodiment, associations between IP addresses and their assignment are stored in a database. IP addresses are read and semi-authoritative sources (e.g., DNS servers) are queried for information about the IP addresses. Information received in response to the query may be used to validate the IP address (e.g., in a network, all IP addresses used for VM instances will have a corresponding URL in a specific format).

Abstract: A conveyor apparatus comprising an elongated endless flexible conveyor belt having a moulded ridged conformation on its inner surface mounted between a drive roller drum and a take up roller drum, two elongated conveyor side plates and a plurality of idle conveyor rollers, wherein the diameter of the drive roller drum and the take up roller drum is uniform throughout their length.

Abstract: One example of a video monitoring system includes a frame acquisition subsystem, a stage gate motion detection subsystem, a person detection subsystem, a face recognition subsystem, and an alert emission subsystem. The frame acquisition subsystem extracts frames from an input video. The stage gate motion detection subsystem separates background motion from foreground motion within frames. The person detection subsystem detects people including faces and bodies within the foreground motion. The face recognition subsystem matches detected faces to previously registered users. The alert emission subsystem provides alerts based on events detected by the stage gate motion subsystem, the person detection subsystem, and the face recognition subsystem.

Abstract: Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches.

Abstract: An example control system includes a memory and at least one processor to obtain image data from a given region and perform image analysis on the image data to detect a set of objects in the given region. For each object of the set, the example Memory control system may classify each object as being one of multiple predefined classifications of object permanency, including (i) a fixed classification, (ii) a static and fixed classification, and/or (iii) a dynamic classification. The control system may generate at least a first layer of a occupancy map for the given region that depicts each detected Instructions To Perform object that is of the static and fixed classification and excluding each detected object that is either of the static and unfixed classification or of the dynamic classification.

Abstract: An example robot performs a scan to obtain image data of a given region. The robot performs image analysis on the image data to detect a set of undesirable objects, and generates a reference map that excludes the set of undesirable objects, where the reference map is associated with the location of the robot at the time of the scan.

Abstract: Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches.

Abstract: In some aspects, the disclosure is directed to methods and systems for utilizing a thin-film bulk acoustic resonator (FBAR) as a frequency reference for a phase-locked loop (PLL) circuit controlling frequency of a voltage controlled oscillator (VCO). In some implementations, the FBAR-based oscillator may be used as a reference to an analog or digital PLL circuit (either directly, or divided to a lower frequency). In other implementations, the FBAR-based oscillator may be used as a reference to a mixing-based PLL rather than a dividing-based PLL. Through these implementations, the noise contribution of many of the PLL circuit components or elements may be reduced (e.g. noise from a delta-sigma modulator (DSM), multiple modulus divider (MMD), phase frequency detector (PFD)/charge pump (CP), etc.).

Abstract: According to examples, an apparatus may include a processor and a memory on which is stored machine readable instructions that are to cause the processor to determine a reference frame from a plurality of frames received at multiple different times, in which each of the plurality of frames includes audio signal data, and in which the reference frame includes audio signal data that identifies a highest audio signal level among audio signals identified in the plurality of frames. The reference frame may be time-aligned with each of the plurality of frames other than the reference frame to obtain respective time-aligned frames. The audio signals identified in each of the respective time-aligned frames may be added together to generate respective added audio signals. The respective added audio signals may be combined together to obtain a combined audio signal and the combined audio signal may be outputted.

Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.

Abstract: According to examples, an apparatus may include a processor and a memory on which is stored machine readable instructions that are to cause the processor to determine a reference frame from a plurality of frames received at multiple different times, in which each of the plurality of frames includes audio signal data, and in which the reference frame includes audio signal data that identifies a highest audio signal level among audio signals identified in the plurality of frames. The reference frame may be time-aligned with each of the plurality of frames other than the reference frame to obtain respective time-aligned frames. The audio signals identified in each of the respective time-aligned frames may be added together to generate respective added audio signals. The respective added audio signals may be combined together to obtain a combined audio signal and the combined audio signal may be outputted.

Abstract: Systems, devices, and methods for a plush toy having an outer surface; one or more male interlocking buttons disposed on the outer surface of the plush toy; and one or more female interlocking buttons disposed on the outer surface of the plush toy; wherein the one or more male interlocking buttons and the one or more female interlocking buttons form an interlocked pair when the one or more male interlocking buttons are detachably attached to the one or more female interlocking buttons; where detachably attaching the one or more male interlocking buttons to the one or more female interlocking buttons produces an audible sound; and where the interlocked pair forms a closed loop configured to secure the plush toy about an external object.

Abstract: A privacy protection device may include a disabling module to prevent at least one sensor on an always-on device from sensing input and an activation sensor to detect when the at least one sensor is to be activated on the always-on device, wherein the disabling module is integrated into the always-on device

Abstract: One example of a video monitoring system includes a frame acquisition subsystem, a stage gate motion detection subsystem, a person detection subsystem, a face recognition subsystem, and an alert emission subsystem. The frame acquisition subsystem extracts frames from an input video. The stage gate motion detection subsystem separates background motion from foreground motion within frames. The person detection subsystem detects people including faces and bodies within the foreground motion. The face recognition subsystem matches detected faces to previously registered users. The alert emission subsystem provides alerts based on events detected by the stage gate motion subsystem, the person detection subsystem, and the face recognition subsystem.