Patents by Inventor David A. Schroter
David A. Schroter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10261791Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.Type: GrantFiled: February 24, 2017Date of Patent: April 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian R. Prasky, David A. Schroter, Chung-Lung K. Shum, Corey C. Stappenbeck
-
Patent number: 10108426Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.Type: GrantFiled: September 1, 2015Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Steven R. Carlough, Lee E. Eisen, David A. Schroter
-
Patent number: 10102002Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.Type: GrantFiled: September 30, 2014Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Steven R. Carlough, Lee E. Eisen, David A. Schroter
-
Publication number: 20180246723Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Inventors: Brian R. Prasky, David A. Schroter, Chung-Lung K. Shum, Corey C. Stappenbeck
-
Patent number: 9880847Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.Type: GrantFiled: June 26, 2015Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Brian D. Barrick, Lee E. Eisen, David A. Schroter
-
Publication number: 20160378489Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Gregory W. Alexander, Brian D. Barrick, Lee E. Eisen, David A. Schroter
-
Publication number: 20160092212Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.Type: ApplicationFiled: September 30, 2014Publication date: March 31, 2016Inventors: GREGORY W. ALEXANDER, STEVEN R. CARLOUGH, LEE E. EISEN, DAVID A. SCHROTER
-
Publication number: 20160092233Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.Type: ApplicationFiled: September 1, 2015Publication date: March 31, 2016Inventors: GREGORY W. ALEXANDER, STEVEN R. CARLOUGH, LEE E. EISEN, DAVID A. SCHROTER
-
Patent number: 9104399Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.Type: GrantFiled: December 23, 2009Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
-
Patent number: 9075600Abstract: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.Type: GrantFiled: June 24, 2010Date of Patent: July 7, 2015Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter
-
Patent number: 8549255Abstract: A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.Type: GrantFiled: February 15, 2008Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: David A. Schroter, Mark S. Farrell, Jennifer Navarro, Chung-Lung Kevin Shum, Charles F. Webb
-
Publication number: 20110320782Abstract: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter
-
Patent number: 8082467Abstract: A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.Type: GrantFiled: December 23, 2009Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Fadi Busaba, David A. Schroter, Eric Schwarz, Brian W. Thompto, Wesley J. Ward, III
-
Publication number: 20110154107Abstract: A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Applicant: International Business Machines CorporationInventors: GREGORY W. ALEXANDER, Fadi Busaba, David A. Schroter, Eric Schwarz, Brian W. Thompto, Wesley J. Ward, III
-
Publication number: 20110153991Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Applicant: International Business Machines CorporationInventors: FADI BUSABA, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
-
Patent number: 7966474Abstract: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.Type: GrantFiled: February 25, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Chung-Lung Kevin Shum, Fadi Y. Busaba, Mark S. Farrell, Bruce C Giamei, Bernd Nerz, David A. Schroter, Charles F. Webb
-
Publication number: 20090217009Abstract: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung-Lung Kevin Shum, Fadi Y. Busaba, Mark S. Farrell, Bruce C. Giamei, Bernd Nerz, David A. Schroter, Charles F. Webb
-
Publication number: 20090210662Abstract: A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David A. Schroter, Mark S. Farrell, Jennifer Navarro, Chung-Lung Kevin Shum, Charles F. Webb
-
Publication number: 20080109640Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.Type: ApplicationFiled: January 16, 2008Publication date: May 8, 2008Applicant: International Business Machines CorporationInventors: William Burky, Ronald Kalla, David Schroter, Balaram Sinharoy
-
Patent number: 7363625Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.Type: GrantFiled: April 24, 2003Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: William E. Burky, Ronald N. Kalla, David A. Schroter, Balaram Sinharoy