Abstract: A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

Abstract: A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Abstract: A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.

Abstract: A method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor provides a mechanism for redistributing rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper.

Abstract: A method and multithreaded processor for dynamically sharing an interrupt handling logic unit among multiple threads. A first and second state unit may be configured to determine whether an interrupt was generated from a first thread and a second thread, respectively. An arbiter may be coupled to the first and second state units. A shared interrupt handling logic unit may be coupled to the arbiter where the shared interrupt handling logic unit may be configured to handle interrupts generated from the first and second threads. Upon a state unit, e.g., first state unit, second state unit, determining an interrupt was generated from a particular thread, the state unit may request control of the interrupt handling logic unit from the arbiter. The arbiter may grant the request from the state unit if the interrupt handling logic unit is available to handle the interrupt detected.

Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.

Abstract: An apparatus for fetching instructions in a computer system is disclosed. The apparatus includes a cache circuit for holding a sub-set of main store, a buffer circuit for holding instructions fetched from the cache for dispatch to a plurality of execution units, and a branch resolution unit. A first tag associated with each instruction to be dispatched is generated that identifies the instruction while it is in process. The execution units execute dispatched instructions and provide resulting condition codes and first tag for each instruction that is completed. The branch resolution unit, fetches a not guessed instruction stream from the cache such that the not guessed instruction stream is available to the instruction buffer during the same cycle that the guess is resolved. The branch resolution unit also includes means for guessing the result of a branch instruction and means for fetching a guessed instruction stream to be fetched.

Abstract: A method and apparatus for supporting speculative execution of count and link register modifying instructions in a microprocessor is provided. The apparatus includes a queue of rename buffers storing count/link register operand data resulting from speculatively executed instructions that modify a count/link register. The queue contains a set of control buffers, wherein each control buffer contains control bits associated with a rename buffer, the control bits including an instruction identifier tag identifying a speculatively executed instruction, the operand data of the speculatively executed instruction being stored in the associated rename buffer, and an available bit indicating when the operand data no longer needs to be stored in the associated rename buffer.

Abstract: In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event that a next sequential instruction requires the contents of one of the registers in the subset, the number of the required register is compared with the incremented number and the decoding phase of the next instruction is allowed to proceed when the required register has been loaded as indicated by the incremented number. The identity of the highest numbered and the next to highest numbered registers loaded by the LMR instruction are recorded in a target register and an exclusive or-circuit is provided to determine whether the total number of registers loaded by the LMR instruction is an even number or an odd number.

Abstract: This disclosure describes an efficient method of moving data from one location in memory to another without caching the data. This includes data transfers from one main storage location to another, transfers between main and expanded storage, and transfers from one expanded storage location to another.