Patents by Inventor David A. Secker
David A. Secker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096387Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: September 1, 2023Publication date: March 21, 2024Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Patent number: 11907555Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: November 18, 2022Date of Patent: February 20, 2024Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Publication number: 20240020258Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: July 20, 2023Publication date: January 18, 2024Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Patent number: 11783879Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: GrantFiled: November 19, 2021Date of Patent: October 10, 2023Assignee: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20230299668Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Inventors: Sanjay Dabral, David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao
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Patent number: 11755521Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: GrantFiled: June 29, 2022Date of Patent: September 12, 2023Assignee: Rambus Inc.Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Patent number: 11699949Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.Type: GrantFiled: July 23, 2021Date of Patent: July 11, 2023Assignee: Apple Inc.Inventors: Sanjay Dabral, David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao
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Publication number: 20230138512Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: ApplicationFiled: November 18, 2022Publication date: May 4, 2023Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Publication number: 20220398206Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: June 29, 2022Publication date: December 15, 2022Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Patent number: 11520508Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: May 21, 2020Date of Patent: December 6, 2022Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 11409682Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: GrantFiled: November 17, 2020Date of Patent: August 9, 2022Assignee: Rambus Inc.Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Patent number: 11398692Abstract: The connector portion of a flex connector may be integrated into a socket, by forming a complete cutout in the socket in which the connector is located, or by forming the socket with a portion having a reduced thickness relative to the rest of the socket, with the connector being positioned in this portion of reduced thickness between the socket and an MLB. Another flex connector may be formed vertically above the first flex connector, mounted to the top surface of the package and clamped in place by a heat sink on top of the stack. Providing both top and bottom flex connectors may multiply the number of available connections for a given footprint. A heatsink positioned on top of the stack may include a spring assembly on a bottom portion to engage specified portions of the stack with a predefined force to ensure correct loading.Type: GrantFiled: September 25, 2020Date of Patent: July 26, 2022Assignee: Apple Inc.Inventors: Mahesh S. Hardikar, David A. Secker, Rajasekaran Swaminathan, Ravindranath T. Kollipara, Robert R. Atkinson
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Publication number: 20220172760Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: November 19, 2021Publication date: June 2, 2022Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20220102884Abstract: The connector portion of a flex connector may be integrated into a socket, by forming a complete cutout in the socket in which the connector is located, or by forming the socket with a portion having a reduced thickness relative to the rest of the socket, with the connector being positioned in this portion of reduced thickness between the socket and an MLB. Another flex connector may be formed vertically above the first flex connector, mounted to the top surface of the package and clamped in place by a heat sink on top of the stack. Providing both top and bottom flex connectors may multiply the number of available connections for a given footprint. A heatsink positioned on top of the stack may include a spring assembly on a bottom portion to engage specified portions of the stack with a predefined force to ensure correct loading.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: MAHESH S. HARDIKAR, DAVID A. SECKER, RAJASEKARAN SWAMINATHAN, RAVINDRANATH T. KOLLIPARA, ROBERT R. ATKINSON
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Publication number: 20220014095Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.Type: ApplicationFiled: July 23, 2021Publication date: January 13, 2022Inventors: Sanjay Dabral, David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao
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Patent number: 11211105Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: GrantFiled: August 6, 2020Date of Patent: December 28, 2021Assignee: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Patent number: 11106542Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.Type: GrantFiled: October 4, 2019Date of Patent: August 31, 2021Assignee: Rambus, Inc.Inventors: Steven Woo, David A. Secker, Ravindranath Kollipara
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Patent number: 11101732Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.Type: GrantFiled: July 30, 2020Date of Patent: August 24, 2021Assignee: Apple Inc.Inventors: Sanjay Dabral, David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao
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Publication number: 20210124703Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: November 17, 2020Publication date: April 29, 2021Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Publication number: 20210050043Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: August 6, 2020Publication date: February 18, 2021Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh