Patents by Inventor David A. Secker
David A. Secker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180285013Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: ApplicationFiled: July 14, 2016Publication date: October 4, 2018Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 10026666Abstract: Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.Type: GrantFiled: October 14, 2014Date of Patent: July 17, 2018Assignee: Rambus Inc.Inventors: Nitin Juneja, Wendemagegnehu Beyene, David A. Secker, Ely K. Tsern
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Publication number: 20180089035Abstract: Described is memory system enabling memory minoring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.Type: ApplicationFiled: October 13, 2017Publication date: March 29, 2018Inventors: Steven Woo, David A. Secker, Ravindranath Kollipara
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Publication number: 20180047436Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: June 14, 2017Publication date: February 15, 2018Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Patent number: 9870982Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: GrantFiled: October 3, 2016Date of Patent: January 16, 2018Assignee: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Patent number: 9841791Abstract: A rack unit configuration is described that includes a first printed circuit board (PCB) assembly interleaved with a second PCB assembly that is inverted with respect to the first PCB assembly. The configuration of the first PCB assembly and the second PCB assembly allow for increased component and power densities within computing systems, memory systems, etc. The increased density may be achieved while allowing sufficient mechanical clearance to allow easy component replacement and servicing (e.g., and hot pluggability). Power density may also be increased with PCB assemblies including nested and interleaved power modules.Type: GrantFiled: December 12, 2014Date of Patent: December 12, 2017Assignee: Rambus Inc.Inventors: Donald R. Mullen, Chi-Ming Yeung, David A. Secker
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Patent number: 9804931Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.Type: GrantFiled: December 12, 2014Date of Patent: October 31, 2017Assignee: Rambus Inc.Inventors: Steven Woo, David Secker, Ravindranath Kollipara
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Patent number: 9798628Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.Type: GrantFiled: December 12, 2014Date of Patent: October 24, 2017Assignee: Rambus Inc.Inventors: Steven Woo, David Secker, Ravindranath Kollipara
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Patent number: 9734879Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: GrantFiled: July 29, 2015Date of Patent: August 15, 2017Assignee: RAMBUS INC.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20170098595Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: ApplicationFiled: October 3, 2016Publication date: April 6, 2017Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Publication number: 20170024348Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: October 10, 2016Publication date: January 26, 2017Inventors: AMIR AMIRKHANY, SURESH RAJAN, RAVINDRANATH KOLLIPARA, IAN SHAEFFER, DAVID A. SECKER
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Patent number: 9498951Abstract: An inkjet nozzle device includes: a nozzle chamber having a floor, a roof and perimeter sidewalls extending between the floor and the roof, wherein a nozzle aperture is defined in the roof; a heating element for generating gas bubbles in the nozzle chamber so as to eject ink through the nozzle aperture, wherein a centroid of the heating element is aligned with a centroid of the nozzle aperture; and a pair of chamber inlets defined in the floor of the nozzle chamber, the chamber inlets being symmetrically disposed about the centroid of the heating element. The inkjet nozzle device has a pair of orthogonal symmetry planes passing through the centroid of the nozzle aperture.Type: GrantFiled: February 20, 2015Date of Patent: November 22, 2016Assignee: Memjet Technology LimitedInventors: Sam Mallinson, Philip Palma, David Secker, Paul Reichl, Glenn Horrocks, Angus North
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Patent number: 9489323Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: GrantFiled: February 18, 2014Date of Patent: November 8, 2016Assignee: Rambus Inc.Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Patent number: 9466568Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.Type: GrantFiled: April 9, 2015Date of Patent: October 11, 2016Assignee: Rambus Inc.Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
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Publication number: 20160291894Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.Type: ApplicationFiled: February 23, 2016Publication date: October 6, 2016Inventors: Chi-Ming YEUNG, David SECKER, Ravindranath KOLLIPARA, Shajith Musaliar SIRAJUDEEN, Yoshie NAKABAYASHI
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Publication number: 20160259739Abstract: A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.Type: ApplicationFiled: February 19, 2016Publication date: September 8, 2016Inventors: Steven WOO, David SECKER
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Patent number: 9298228Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.Type: GrantFiled: July 27, 2015Date of Patent: March 29, 2016Assignee: Rambus Inc.Inventors: Abhijit M. Abhyankar, Ravindranath Kollipara, Thomas J. Giovannini, Ming Li, David A. Secker, Arun Vaidyanath, Donald R. Mullen, Adrian F. Torres
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Publication number: 20150332746Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20150309899Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.Type: ApplicationFiled: December 12, 2014Publication date: October 29, 2015Inventors: Steven WOO, David SECKER, Ravindranath KOLLIPARA
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Publication number: 20150309529Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.Type: ApplicationFiled: December 12, 2014Publication date: October 29, 2015Inventors: Steven WOO, David SECKER, Ravindranath KOLLIPARA