Patents by Inventor David A. White

David A. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8043448
    Abstract: Disclosed herein are zirconium-based alloys that may be fabricated to form nuclear reactor components, particularly fuel cladding tubes, that exhibit sufficient corrosion resistance and hydrogen absorption characteristics, without requiring a late stage ?+? or ?-quenching processes. The zirconium-base alloys will include between about 1.30-1.60 wt % tin; 0.0975-0.15 wt % chromium; 0.16-0.24 wt % iron; and up to about 0.08 wt % nickel, with the total content of the iron, chromium and nickel comprising at least about 0.3175 wt % of the alloy. The resulting components will exhibit a surface region having a mean precipitate sizing of between about 50 and 100 nm and a Sigma A of less than about 2×10?19 hour with the workpiece processing generally being limited to temperatures below 680° C. for extrusion and below 625° C. for all other operations, thereby simplifying the fabrication of the nuclear reactor components while providing corrosion resistance comparable with conventional alloys.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: October 25, 2011
    Assignee: Global Nuclear Fuel-Americas, LLC
    Inventors: David White, Daniel R. Lutz, Yang-Pi Lin, John Schardt, Gerald Potts, Robert Elkins, Hiroaki Kagami, Hideyuki Mukai
  • Publication number: 20110249353
    Abstract: Described herein are buckled structures useful for forming specific and precise optical shapes. For example, buckled structures are disclosed which have parabolic, near-parabolic, cylindrical, near cylindrical, conic section shapes, arcs and other non-sinusoidal optical curves. Also described herein are buckled structures including one or more restraints for forcing the structures to adopt or maintain specific optical shapes upon or after buckling. In another aspect, provided herein are methods for forming optical structures.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 13, 2011
    Inventor: David WHITE
  • Publication number: 20110245747
    Abstract: A splint for treatment of a joint including a generally longitudinal body including first and second portions forming inner and outer splint layers, with the second portion being rollable onto the first portion to form the splint. The outer splint layer may include a longitudinal cavity for insertion of a stay, and/or may include a fluted section for permitting insertion of a stay between the inner and outer splint layers. The longitudinal body may be linear or curved. The first and second portions may include areas having different thicknesses for adding rigidity to the splint structure at a predetermined location. The splint may include a cutout for exposing a predetermined portion of a user's finger. The splint may be made of a flexible material such as rubber, silicone and/or urethane. The splint may include a reduced friction surface layer for minimizing sticking of the splint during donning.
    Type: Application
    Filed: February 22, 2011
    Publication date: October 6, 2011
    Inventors: Ronit Wollstein, Thomas Ogden, Jonathan Pearlman, Rory A. Cooper, David White, Miriam Zisook
  • Publication number: 20110231879
    Abstract: A data modeling method for modeling data for an electronic program guide (EPG) at a broadcast headend is described.
    Type: Application
    Filed: May 24, 2011
    Publication date: September 22, 2011
    Applicant: NDS Limited
    Inventors: David White, Ian Bastable, Martin Gold
  • Patent number: 8023805
    Abstract: A method for switching from playing a first compressed data segment to playing a second compressed recorded data segment, the method including playing an uncompressed copy of a start of the second compressed recorded data segment upon switching from playing the first compressed data segment, decoding the second compressed recorded data segment from a preceding random access point, the preceding random access point preceding, in the second compressed recorded data segment, a point at which playing is to be switched to the second compressed recorded data segment, stopping the decoding of the second compressed recorded data segment when reaching a point beyond a point currently being played in the uncompressed copy, and switching to playing the second compressed recorded data segment when playing the uncompressed copy of a start of the second compressed recorded data segment reaches the point at which the decoding of the second compressed recorded data segment was stopped.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: September 20, 2011
    Assignee: NDS Limited
    Inventors: David White, Kevin A. Murray, Ezra Darshan, Moshe Shlissel, David Fink, David Whittaker, Zeev Geyzel, Reuven Wachtfogel
  • Patent number: 8001512
    Abstract: A method, system, and computer program product are disclosed for using pattern-dependent models at early stages of the design process. This addresses the key disadvantage of prior approaches which are restricted to using such models later in the design process for IC designs that are nearly complete. Pattern-dependent manufacturing effects are extracted from early stage designs and using the extracted pattern-dependent effects to efficiently and effectively design the integrated circuit. One or more contexts are built around one or more units of the design, with examples of units being a block or cell. The units are then used in the context to generate pattern-dependent data as a basis for one or more pattern-dependent models.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 16, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventor: David White
  • Patent number: 8001516
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 16, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Publication number: 20110171205
    Abstract: The invention provides isolated nucleic acids molecules, designated 15571, 2465, 14266, 2882, 52871, 8203 or 16852 nucleic acid molecules. The invention also provides antisense nucleic acid molecules, recombinant expression vectors containing 15571, 2465, 14266, 2882, 52871, 8203 or 16852 nucleic acid molecules, host cells into which the expression vectors have been introduced, and nonhuman transgenic animals in which a 15571, 2465, 14266, 2882, 52871, 8203 or 16852 gene has been introduced or disrupted. The invention still further provides isolated 15571, 2465, 14266, 2882, 52871, 8203 or 16852 proteins, fusion proteins, antigenic peptides and anti-15571, 2465, 14266, 2882, 52871, 8203 or 16852 antibodies. Diagnostic and therapeutic methods utilizing compositions of the invention are also provided.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 14, 2011
    Applicant: Millennium Pharmaceuticals, Inc.
    Inventors: Martin R. Hodge, Clare M. Lloyd, Nadine S. Weich, Jose M. Lora, David White, Maria A. Glucksmann, Keith E. Robison, Inmaculada Silos-Santiago, Andrew D.J. Goodearl, Rory A.J. Curtis
  • Patent number: 7964063
    Abstract: The present invention relates to methods for making modified fillers for use in a papermaking process, methods for making a paper using the modified fillers, and modified fillers and paper produced therewith. In one aspect, the present invention provides a method for making a modified filler for use in a papermaking process, which comprises applying a starch composition comprising starch to a reaction composition comprising at least one of fatty acid, rosin acid, and ammonium sulfate to form a reaction mixture; and applying a filler composition comprising a filler to the reaction mixture, whereby forming a modified filler. In another aspect, the present invention provides a method of using a modified filler in a papermaking process, which comprises applying a modified filler to a composition comprising fiber to form a mixture; and processing the mixture, whereby producing a paper.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: June 21, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Yulin Deng, Se-Young Yoon, Arthur Ragauskas, David White
  • Patent number: 7962867
    Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: June 14, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7962866
    Abstract: Disclosed are an improved method, system, and computer program product for a method or system with concurrent models to more accurately determine and represent the three-dimensional design features of electronic designs. Some embodiments disclose a method or a system for determining the design feature characteristics based upon their respective three-dimensional profiles. Some other embodiments further determine whether the design objectives or constraints are met or may be relaxed based upon the design feature characteristics in order to complete the design. Other embodiments store the profile or geometric characteristics, or information derived therefrom, in a database associated with the design to reduce the need for potentially expensive computations. The method or system may modify the designs or the processes to reflect whether the design objectives or constraints are met or relaxed.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: June 14, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Louis K. Scheffer
  • Publication number: 20110126235
    Abstract: A method and system of optimizing strings comprised in program guide data for transmission is described. The method includes sharing, in the program guide data, a plurality of strings, each string among the plurality of strings including a shared sorting key, implementing an order access of a sorted sharing index, wherein the program guide data and the shared sorting key are comprised in the same data storage structure. Related methods and apparatus are also described.
    Type: Application
    Filed: December 20, 2010
    Publication date: May 26, 2011
    Applicant: NDS Limited
    Inventors: David White, Ian Bastable, Martin Gold, Anthony Platt
  • Patent number: 7937674
    Abstract: Disclosed is an improved method, system, and computer program product for predicting and improving the integrity, manufacturability, reliability, and performance of an electronic circuit feature based on the stresses or strains of design features of electronic designs. Some embodiments identify the design, the concurrent model(s), design feature physical or electrical parameters or attributes, analyzes the stresses or strains to predict the integrity of the design and determines whether the design meets the design objectives or constraints. Some other embodiments make corrections to the designs or the processes based upon the determination of whether the design meets the design objectives or constraints. Some other embodiments compute the variations of the design features as a result of the stresses or strains and determine their impact on the subsequent processes.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 3, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Louis K. Scheffer
  • Publication number: 20110093826
    Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.
    Type: Application
    Filed: December 27, 2010
    Publication date: April 21, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: David WHITE, Eric NEQUIST
  • Publication number: 20110087718
    Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.
    Type: Application
    Filed: October 28, 2010
    Publication date: April 14, 2011
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Uma Srinivasan, Stephen David White
  • Publication number: 20110087717
    Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.
    Type: Application
    Filed: October 28, 2010
    Publication date: April 14, 2011
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Uma Srinivasan, Stephen David White
  • Publication number: 20110077687
    Abstract: Provided herein are systems, devices and methods for the correction of spinal deformities with the use one or more implantable rods configured to apply a corrective force to the spine. Methods of minimally invasive implantation of a corrective system are provided, such as where the corrective system is attached only to the spinous process of one or more vertebral bodies. Various corrective systems as well as components thereof are also provided, such as those that allow limited movement with respect to the spinal column.
    Type: Application
    Filed: June 8, 2010
    Publication date: March 31, 2011
    Inventors: Matthew Thompson, Hiram Chee, Richard Ginn, Darin Gittings, Ivan Sepetka, David White
  • Publication number: 20110071568
    Abstract: Spacer devices for treating spinal stenosis are provided herein, as are methods for using the same. In some example embodiments, these devices are configured for attachment over or through the interspinous ligaments. These devices generally include a spacer portion and an attachable retainer. Also provided are systems for the delivery of the spacer devices and methods for using the same.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 24, 2011
    Inventors: Richard S. Ginn, Robert Elliott DeCou, Nicanor Domingo, Hans F. Valencia, David A. White, Scott Yerby
  • Publication number: 20110046767
    Abstract: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.
    Type: Application
    Filed: October 29, 2010
    Publication date: February 24, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Louis K. Scheffer, David White
  • Patent number: D634229
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: March 15, 2011
    Assignee: Brijot Imaging Systems, Inc.
    Inventors: Mark C. Williams, Reeder Noah Ward, Kenneth David White, Jamie Ruth White, James H. Muir