Abstract: A method of delivering a receptacle to an instrument includes the steps of supporting a receptacle containing a fluid on a carrier, transporting the carrier supporting the receptacle on a conveyor extending adjacent to each of a plurality of instruments, transferring the receptacle from the carrier to a puck supported on a carriage when the carriage is positioned at a first location, moving the carriage with the receptacle seated in the puck from the first location to a second location within an instrument of the plurality of instruments, and drawing at least a portion of the fluid from the receptacle seated in the puck into a tip associated with a fluid extraction device of the instrument when the carriage is positioned at the second location.

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: In one embodiment, a microfluidic device has a substrate that defines a first inlet for a continuous phase fluid, a second inlet for a dispersed phase fluid, and droplet generators that can produce micro-droplets from the continuous and dispersed phase fluids. The substrate defines (i) a plurality of delivery channels in fluid communication with the first and second inlets, each delivery channel having a first dimension along a first plane that is perpendicular to a transverse direction, and (ii) a plurality of trenches that extend from the delivery channels towards the droplet generators along the transverse direction. Each trench has a second dimension along a plane that is perpendicular to the transverse direction that is smaller than the first dimension. The substrate defines a plurality of vias that extend from the trenches to the droplet generators so as to fluidly connect the delivery channels with the droplet generators.

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including obtaining, from a host system, a power safety configuration for a partition, wherein the power safety configuration for the partition configures the memory device to implement power safe writing for the partition by operating in a first write mode utilizing single level cell (SLC) caching, or to implement non-power safe writing for the partition by operating in a second write mode without utilizing SLC caching, and configuring the memory device to operate in the first write mode or the second write mode based on the power safety configuration.

Abstract: A method for monitoring an IoT network receives a first user input from a user, the first user input comprising a selection of a machine learning model associated with an activity, and a second user input from the user, the second user input comprising a selection of one or more attributes of a set of attributes associated with an asset. User created rules define an asset behavior. The rules are input by the user in a human-readable language. Information representing the asset type and asset behavior is associated with one or more physical devices associated with a node of the network. Data indicative of a current state of the asset, the current state of the asset indicative of at least one attribute of the asset, is received and processed in the machine learning model to determine whether a notification should be provided.

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Abstract: A method is provided for performing dynamic inferencing at a node configured to communicate with other nodes of an IoT hierarchy. In the method, a schema for an asset object associated with one or more of at least one physical process and at least one physical device is received at the node. The schema is formatted according to an inferencing engine model format. An artificial intelligence model capable of being executed in an inferencing engine is received at the node. Data indicative of one or more of a current state of at least one physical process and a current state of at least one physical device is received at the node. The received data according to the schema and an inferencing engine are processed at the node. The inferencing engine generates a new predictive attribute based on the set of attributes, and the processing normalizes the received data according to the schema to generate normalized data, the normalized data includes the predictive attribute from the inferencing engine.

Abstract: The present disclosure concerns promoters engineered to increase their responsiveness to a C2 carbon source. The engineered promoters include at least one external carbon source-responsive element (CSRE) located upstream and proximal to the transcription start site of a gene operatively associated thereto. The engineered promoters can be used in a heterologous nucleic acid molecule, a vector, or an expression cassette to promote the expression of a gene in a microbe. The present disclosure also concerns a method for generating the engineered promoters as well as a method for expressing a gene in a recombination microbial host cell using the engineered promoter(s).

Abstract: A fuel is mixed with an oxidant to form a first combustible gas mixture having predominantly non-plug flow. The first combustible gas mixture is transitioned into a second combustible gas mixture having predominantly plug flow. The second combustible gas mixture may be combusted to form one or more combustion products. The one or more combustion products may be mixed with a feedstock to cause the feedstock to decompose.

Abstract: There is described a method of producing hydrogen and nitrogen using a feedstock gas reactor. Reaction of feedstock and combustion gases in the reactor produces hydrogen and nitrogen through pyrolysis of the feedstock gas. Parameters of the process may be adjusted to control the ratio of hydrogen to nitrogen that is produced such that it may be suitable, for example, for the synthesis of ammonia.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: In some implementations, a memory apparatus may compress a physical page table associated with a logical-to-physical (L2P) table, to obtain a compressed version of the physical page table, wherein the physical page table is associated with logical block address (LBA) and physical address pairs, wherein the compressed version is associated with a set of groups of LBAs and an exception list, and wherein the compressed version includes an indication of physical addresses associated with respective starting LBAs included in the set of groups and includes sequentiality indications for respective groups from the set of groups. The memory apparatus may receive, from a host system, a command indicating an LBA that is associated with the physical page table. The memory apparatus may perform a lookup operation using the compressed version of the physical page table to identify a physical address associated with the LBA.

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

Abstract: Systems and methods for performing fund transfers at an automated teller machine (ATM) are disclosed. The systems and methods include using authentication transaction keys to enable a transferee device to facilitate an ATM withdrawal. The fund transfer is based on pre-defined ATM transaction parameters, which include an amount of funds for the transaction and a geographic limitation for an ATM at which the transaction may occur. Funds can be transferred in response to authentication of the authentication transaction key and confirmation that the ATM corresponds to the geographic limitation for the ATM.

Abstract: Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer.

Abstract: In some implementations, a memory apparatus may receive a command indicating a logical block address (LBA) that is associated with a logical-to-physical (L2P) table. The memory apparatus may perform a lookup operation associated with a compressed version of an address range of the L2P table to identify a physical address in non-volatile memory associated with the LBA, wherein the compressed version is stored in a volatile memory of the memory apparatus, wherein the compressed version is associated with an exception list that indicates physical addresses for respective LBAs, included in the address range, that are associated with non-sequential physical addresses, and wherein the compressed version is associated with a binary tree that indicates locations in the exception list associated with the respective LBAs. The memory apparatus may perform, based on the command, an action associated with the physical address.