Abstract: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.

Abstract: An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.

Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

Abstract: A method of isolating sources of variance in parametric data includes steps of: (a) cleaning a data set of measurements for a plurality of parameters; (b) generating a principal component analysis basis from the cleaned data set; (c) estimating an independent component analysis model from the principal component analysis basis; (d) calculating percentages of variance for the plurality of parameters explained by each component in the estimated independent component analysis model; (e) if the calculated percentages of variance indicate that a component is a minor component, then transferring control to step (f), else transferring control to step (g); (f) removing the minor component from the principal component analysis basis and transferring control to step (c); and (g) generating as output the estimated independent component analysis model wherein no component of the independent component analysis model is a minor component.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout design for the layer then is divided into separate areas or “windows,” and a target density for each window is determined. More particularly, each window is analyzed to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. In some implementations, the target density will be the smallest density that will comply with each of the specified density value constraints. Once the target density for the window has been determined, the fill polygons required to most closely approach this target density are selected and added to the circuit layout design.

Abstract: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.

Abstract: A method of manufacturing, e.g., integrated circuits, and of managing a manufacturing process. Product unit (circuit) variation data is collected from clustered product units (wafer sites). Collected data is grouped according to a selected manufacturing parameter. Each group is normalized for the selected manufacturing parameter. Normalized groups are combined. Normalized process data is checked for variances and the data is regrouped and renormalized until variances are no longer found. Each identified variance is correlated with a likely source. Then, each said likely source is addressed, e.g., a tool is adjusted or replaced, to minimize variances.

Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.

Abstract: A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.

Abstract: A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: A method of isolating sources of variance in parametric data includes steps of: (a) cleaning a data set of measurements for a plurality of parameters; (b) generating a principal component analysis basis from the cleaned data set; (c) estimating an independent component analysis model from the principal component analysis basis; (d) calculating percentages of variance for the plurality of parameters explained by each component in the estimated independent component analysis model; (e) if the calculated percentages of variance indicate that a component is a minor component, then transferring control to step (f), else transferring control to step (g); (f) removing the minor component from the principal component analysis basis and transferring control to step (c); and (g) generating as output the estimated independent component analysis model wherein no component of the independent component analysis model is a minor component.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: A method for adaptively providing parametric limits to identify defective die quantizes the die into a plurality of groups according to statistical distributions, such as intrinsic speed in one embodiment. For each quantization level, an intrinsic distribution of the parameter is derived. Adaptive screening limits are then set as a function of the intrinsic distribution. Dies are then screened according to their parametric values with respect to the adaptive limits.