Patents by Inventor David Abercrombie
David Abercrombie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7174281Abstract: A method of manufacturing, e.g., integrated circuits, and of managing a manufacturing process. Product unit (circuit) variation data is collected from clustered product units (wafer sites). Collected data is grouped according to a selected manufacturing parameter. Each group is normalized for the selected manufacturing parameter. Normalized groups are combined. Normalized process data is checked for variances and the data is regrouped and renormalized until variances are no longer found. Each identified variance is correlated with a likely source. Then, each said likely source is addressed, e.g., a tool is adjusted or replaced, to minimize variances.Type: GrantFiled: May 1, 2002Date of Patent: February 6, 2007Assignee: LSI Logic CorporationInventor: David Abercrombie
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Patent number: 7137098Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.Type: GrantFiled: August 27, 2004Date of Patent: November 14, 2006Assignee: LSI Logic CorporationInventors: Bruce J. Whitefield, David A. Abercrombie, David R. Turner, James N. McNames
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Publication number: 20060191634Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.Type: ApplicationFiled: May 12, 2006Publication date: August 31, 2006Inventors: Bruce Whitefield, David Abercrombie
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Patent number: 7062415Abstract: A method for determining outlier data points in. A subset of dataset patterns is selected from a set of mathematical dataset patterns, and the subset of dataset patterns is combined into a composite dataset. The composite dataset is compared to the dataset, and a degree of correlation between the composite dataset and the dataset is determined. Data points within the composite dataset are selectively weighted to improve the degree of correlation, and the steps described above are selectively iteratively repeated until the degree of correlation is at least a desired value. Residuals for the data points within the composite dataset are selectively determined. At least one of the weighted data points within the composite dataset that are weighted within a first specified range, and data points within the composite dataset that have a residual within a second specified range, are selectively output as outlier data points.Type: GrantFiled: August 27, 2004Date of Patent: June 13, 2006Assignee: LSI Logic CorporationInventors: Bruce J. Whitefield, David A. Abercrombie, David R. Turner, James N. McNames
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Publication number: 20060094246Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.Type: ApplicationFiled: November 3, 2004Publication date: May 4, 2006Inventors: Bruce Whitefield, David Abercrombie
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Patent number: 7039556Abstract: A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.Type: GrantFiled: June 14, 2004Date of Patent: May 2, 2006Assignee: LSI Logic CorporationInventors: Bruce J. Whitefield, David A. Abercrombie
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Publication number: 20060059452Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.Type: ApplicationFiled: August 27, 2004Publication date: March 16, 2006Inventors: Bruce Whitefield, David Abercrombie, David Turner, James McNames
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Publication number: 20050288896Abstract: A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.Type: ApplicationFiled: June 14, 2004Publication date: December 29, 2005Inventors: Bruce Whitefield, David Abercrombie
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Patent number: 6980917Abstract: A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.Type: GrantFiled: December 30, 2002Date of Patent: December 27, 2005Assignee: LSI Logic CorporationInventors: Mark Ward, David Abercrombie, Larry Kelley
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Publication number: 20050229144Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.Type: ApplicationFiled: March 16, 2004Publication date: October 13, 2005Inventors: Chandra Desu, Nima Behkami, Bruce Whitefield, David Abercrombie, David Sturtevant
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Publication number: 20050145841Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: ApplicationFiled: January 6, 2005Publication date: July 7, 2005Inventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Publication number: 20050132308Abstract: An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.Type: ApplicationFiled: December 15, 2003Publication date: June 16, 2005Inventors: Bruce Whitefield, David Abercrombie
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Patent number: 6880140Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: GrantFiled: June 4, 2003Date of Patent: April 12, 2005Assignee: LSI Logic CorporationInventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Publication number: 20050060336Abstract: A method of isolating sources of variance in parametric data includes steps of: (a) cleaning a data set of measurements for a plurality of parameters; (b) generating a principal component analysis basis from the cleaned data set; (c) estimating an independent component analysis model from the principal component analysis basis; (d) calculating percentages of variance for the plurality of parameters explained by each component in the estimated independent component analysis model; (e) if the calculated percentages of variance indicate that a component is a minor component, then transferring control to step (f), else transferring control to step (g); (f) removing the minor component from the principal component analysis basis and transferring control to step (c); and (g) generating as output the estimated independent component analysis model wherein no component of the independent component analysis model is a minor component.Type: ApplicationFiled: September 15, 2003Publication date: March 17, 2005Inventors: David Abercrombie, Thaddeus Shannon, James McNames
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Publication number: 20040249598Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Patent number: 6807655Abstract: A method for adaptively providing parametric limits to identify defective die quantizes the die into a plurality of groups according to statistical distributions, such as intrinsic speed in one embodiment. For each quantization level, an intrinsic distribution of the parameter is derived. Adaptive screening limits are then set as a function of the intrinsic distribution. Dies are then screened according to their parametric values with respect to the adaptive limits.Type: GrantFiled: July 16, 2002Date of Patent: October 19, 2004Assignee: LSI Logic CorporationInventors: Manu Rehani, Kevin Cota, David Abercrombie, Robert Madge
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Publication number: 20040128630Abstract: A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Mark Ward, David Abercrombie, Larry Kelley
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Patent number: 6658361Abstract: A method for determining an effective fatal defect count based on defects in a plurality of inspected integrated circuits includes acquiring defect information related to defects in the integrated circuits, and assigning defect weight values to each of the defects based on the defect information. The defect weight values are in N number of defect weight value ranges, including a lowest and a highest defect weight value range. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within a defect weight value range n is determined, where n equals one to N.Type: GrantFiled: October 10, 2001Date of Patent: December 2, 2003Assignee: LSI Logic CorporationInventors: Manu Rehani, Ramkumar Vaidyanathan, David A. Abercrombie
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Publication number: 20030208286Abstract: A method of manufacturing, e.g., integrated circuits, and of managing a manufacturing process. Product unit (circuit) variation data is collected from clustered product units (wafer sites). Collected data is grouped according to a selected manufacturing parameter. Each group is normalized for the selected manufacturing parameter. Normalized groups are combined. Normalized process data is checked for variances and the data is regrouped and renormalized until variances are no longer found. Each identified variance is correlated with a likely source. Then, each said likely source is addressed, e.g., a tool is adjusted or replaced, to minimize variances.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Applicant: LSI LOGIC CORPORATIONInventor: David Abercrombie
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Patent number: 5937324Abstract: A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).Type: GrantFiled: March 13, 1998Date of Patent: August 10, 1999Assignee: Motorola, Inc.Inventors: David A. Abercrombie, Rickey S. Brownson, Michael R. Cherniawski