Patents by Inventor David Alan Lilienfeld
David Alan Lilienfeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11764257Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: January 10, 2022Date of Patent: September 19, 2023Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11417759Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: June 6, 2019Date of Patent: August 16, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
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Publication number: 20220130953Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11271076Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: GrantFiled: July 19, 2019Date of Patent: March 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11245003Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: July 19, 2019Date of Patent: February 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11233157Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.Type: GrantFiled: September 28, 2018Date of Patent: January 25, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20210288180Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11069772Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.Type: GrantFiled: December 14, 2018Date of Patent: July 20, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11056586Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: GrantFiled: September 28, 2018Date of Patent: July 6, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almem Losee
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Patent number: 10957759Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.Type: GrantFiled: December 28, 2018Date of Patent: March 23, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20200203476Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200203487Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.Type: ApplicationFiled: December 28, 2018Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20200203477Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200194546Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 10636660Abstract: To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.Type: GrantFiled: December 20, 2018Date of Patent: April 28, 2020Assignee: GENERAL ELECTRIC COMPANYInventors: Reza Ghandi, Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld
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Publication number: 20200105944Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20200105529Abstract: To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.Type: ApplicationFiled: December 20, 2018Publication date: April 2, 2020Inventors: Reza Ghandi, Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld
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Publication number: 20200105925Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 10608079Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (?m).Type: GrantFiled: February 6, 2018Date of Patent: March 31, 2020Assignee: GENERAL ELECTRIC COMPANYInventors: Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov, Peter Almern Losee
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Patent number: 10600649Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.Type: GrantFiled: April 13, 2018Date of Patent: March 24, 2020Assignee: GENERAL ELECTRIC COMPANYInventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee, Reza Ghandi, David Alan Lilienfeld