Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (?m).

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

Abstract: A charge-balanced (CB) diode may include one or more CB layers. Each CB layer may include an epitaxial layer having a first conductivity type and a plurality of buried regions having a second conductivity type. Additionally, the CB diode may include an upper epitaxial layer having the first conductivity type that is disposed adjacent to an uppermost CB layer of the one or more CB layers. The upper epitaxial layer may also include a plurality of junction barrier (JBS) implanted regions having the second conductivity type. Further, the CB diode may include a Schottky contact disposed adjacent to the upper epitaxial layer and the plurality of JBS implanted regions.

Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.

Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.