Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Abstract: An implantable medical device has a therapy module configured to generate a composite pacing pulse including a series of at least two individual pulses. The therapy module is configured to generate the composite pacing pulse by generating a first pulse of the at least two individual pulses by selectively coupling a first portion of a plurality of capacitors to an output signal line and generate a second pulse of the at least two individual pulses by selectively coupling a second portion of the plurality of capacitors to the output signal line.

Abstract: A head unit device for controlling motion of an object includes a chamber filled with a shear thickening fluid (STF) and a piston. The piston is housed within the chamber and exerts pressure against the STF from a force applied to the piston from the object. The STF is configured to have a decreasing viscosity in response to a first range of shear rates and an increasing viscosity in response to a second range of shear rates. The piston includes at least one piston bypass between opposite sides of the piston that controls flow of the STF between the opposite sides of the piston to selectively react with a shear threshold effect of the first range of shear rates or the second range of shear rates.

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: Systems, methods, and apparatuses are described for determining compliance with a plurality of restrictions associated with one or more devices in an organization. First text indicating restrictions may be received, and second text indicating a current configuration of one or more devices may be received. Both sets of text may be processed by, e.g., removing a portion of the text based on a predetermined list of terms and simplifying the text using a lemmatization algorithm. A first vector and second vector may be generated based on the processed sets of text, and each vector may be weighted based on an inverse frequency of words in their respective text. Each vector may be normalized based on semantic analysis. The two vectors may be compared. Based on the comparison, third text corresponding to a portion of the second vector may be generated and transmitted to a third computing device.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.

Abstract: Embodiments of the present disclosure are configured to assess the severity of a blockage in a vessel and, in particular, a stenosis in a blood vessel. In some particular embodiments, the devices, systems, and methods of the present disclosure are configured to assess the severity of a stenosis in the coronary arteries without the administration of a hyperemic agent.

Abstract: Antimicrobial compositions including at least one acid and at least one anionic surfactant are provided. In particular, food contact antimicrobial compositions including at least one acid and at least one anionic surfactant provide a no-rinse compositions efficacious against Norovirus, having acceptable use solution pH that do not require use of personal protective equipment (PPE), are surface compatible and do not leave residues on treated surfaces are provided. Methods of cleaning a surface with the compositions are also provided.

Abstract: An optical system comprises a first optical path configured to supply a first light with a first range of wavelengths; a second optical path configured to supply a second light with a second range of wavelengths shorter than the first range of wavelengths; a third optical path configured to supply a third light with a third range of wavelengths shorter than the second range of wavelengths; an optical I/O unit configured to emit the first light, the second light and the third light to a target and acquire a light from the target; a reference unit configured to split off a reference light from the third light; and a detector that includes a range of detection wavelengths shared with a CARS light and an interference light.

Abstract: Examples of synchronization of a gyroscope in a virtual-reality (VR) environment are described. In some examples, gyroscopic feedback for VR application content may be predicted. In some examples, a time shift corresponding to a physical system lag of a gyroscope may be added to synchronize the gyroscopic feedback with the VR application content. In some examples, the gyroscopic feedback may be applied based on the time shift.

Abstract: A method of on-demand energy delivery to an active suspension system is disclosed. The suspension system includes an actuator body, a hydraulic pump, an electric motor, a plurality of sensors, an energy storage facility, and a controller. The method includes disposing an active suspension system in a vehicle between a wheel mount and a vehicle body, detecting a wheel event requiring control of the active suspension; and sourcing energy from the energy storage facility and delivering it to the electric motor in response to the wheel event.

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

Abstract: Cleaning and/or maintaining operability of sensors, e.g., mounted on vehicles, e.g., autonomously operated vehicles, and systems, methods, and technologies that support the same. The sensor cleaning system can include a first fluid source and a second fluid source, and can also include a plurality of nozzles each coupled to the first fluid source and to the second fluid source and each including an outlet directed at a subset of vehicle sensors. The system can further include a control system with a controller configured to supply a first fluid from the first fluid source to a selected nozzle, or supply a combination of the first fluid from the first fluid source and a second fluid from the second fluid source to a selected nozzle, to thereby clean a subset of sensors. Methods of manufacturing, configuring, and installing such systems are also disclosed.

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.