Patents by Inventor David Anderson

David Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12084400
    Abstract: A composition comprises one or more trimesic acid derivatives of Formula (I) in which R1, R2, and R3 are independently selected from the group consisting of alkyl groups. A polymer composition comprises a composition as described above and a polyolefin polymer. The polymer compositions containing a trimesic acid derivative of Formula (I) exhibit very low haze levels and minimal extraction of the trimesic acid derivative.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: September 10, 2024
    Assignee: Milliken & Company
    Inventors: Daniel Kremer, Hans-Werner Schmidt, Paul Smith, John David Anderson, Suchitra Datta, Keith Keller, Nathan Mehl, Walter Scrivens
  • Patent number: 12086074
    Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: September 10, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Soujanya Narnur, Timothy David Anderson, Mujibur Rahman, Duc Quang Bui
  • Publication number: 20240296129
    Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.
    Type: Application
    Filed: May 9, 2024
    Publication date: September 5, 2024
    Inventors: Naveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
  • Publication number: 20240297167
    Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 5, 2024
    Inventors: Ruilong Xie, Brent A. Anderson, Albert M. Chu, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Reinaldo Vega, David Wolpert
  • Patent number: 12081322
    Abstract: The disclosed technique secures a seed phrase configured to access a digital wallet, which holds private keys to access digital assets on a blockchain. Copies of portions of the seed phrase are stored at multiple electronic devices. The seed phrase can be reconstructed at a particular device by retrieving a necessary and sufficient number of the portions from the other devices. In one example, the portions can be shared among devices when in physical proximity to each other and/or when the devices are authenticated as belonging to the same user, which owns the digital wallet. As such, the seed phrase can be stored securely across multiple devices and retrieved even when one of those devices is lost, damaged, or stolen.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: September 3, 2024
    Assignee: OSOM PRODUCTS, INC.
    Inventors: Gary Anderson, Jason Sean Gagne-Keats, David John Evans, V
  • Patent number: 12077846
    Abstract: This disclosure relates to apparatus and methods for sublimation and deposition of chemicals. In particular aspects, this disclosure relates to apparatus and methods for patterned sublimation and deposition of chemicals for use in matrix assisted laser desorption ionization imaging mass spectrometry (MALDI IMS). In specific aspects, the apparatus comprises a vacuum chamber and a template comprising a planar surface containing the chemical to be sublimed, where the template is located within the vacuum chamber.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 3, 2024
    Assignee: VANDERBILT UNIVERSITY
    Inventors: David Anderson, Eric Spivey, Richard Caprioli
  • Publication number: 20240288440
    Abstract: The present application relates to infectious diseases, pathogenic organisms or pathogenic antigens, and the immune responses that are the body's first line of defense thereto. The application enables medical protocols and products inter alia for treating or preventing or limiting the dissemination of an infectious disease. Methods and compositions are disclosed which employ dIgA for assessing functional immune responses to a pathogen, and in prophylactic or therapeutic compositions. In particular embodiments, the methods and compositions enhance the armamentarium for those charged with managing infectious diseases and populations exposed to highly transmissible and potentially debilitating or fatal pathogens such as those causing epidemics. One particular infectious disease is COVID-19 caused by the virus SARS-COV-2.
    Type: Application
    Filed: October 6, 2021
    Publication date: August 29, 2024
    Inventors: David Anderson, Heidi Drummer, Purnima Bhat, Huy Van
  • Patent number: 12072814
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: August 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
  • Patent number: 12072974
    Abstract: Techniques are described herein that are capable of detecting an algorithmic attack against a hosted artificial intelligence (AI) system based on inputs (e.g., queries) and outputs of the hosted AI system. In a first example, a feature-based classifier model is used to generate a classification score based on features that are derived from numerical representations of the queries and the outputs, and an algorithmic attack is detected based on the classification score being greater than or equal to a score threshold. In a second example, a transformer-based model is used to generate a vector by providing a multivariate time series, which is based on attribute(s) of the inputs and attribute(s) of the outputs, as an input to the transformer-based model, and an algorithmic attack is detected based on a distance between the vector and a point corresponding to a reference vector being less than or equal to a distance threshold.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: August 27, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hyrum Spencer Anderson, Raja Sekhar Rao Dheekonda, William Pearce, Ricky Dee Loynd, James David McCaffrey, Ram Shankar Siva Kumar
  • Publication number: 20240281329
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson, Daniel Brad Wu
  • Publication number: 20240268721
    Abstract: Techniques are disclosed for measuring an analyte in a biological system. A system may include a medical device with an electrochemical sensor configured to sense the concentration of a plurality of analytes present in a biological system. Processing circuitry of the system may retrieve, identify, and process a respective signal from a respective work electrode to determine the concentration of a respective analyte. The system may further include an implantable medical device configured to sense a cardiac electrogram (EGM). In some examples, the system may be configured to determine one or more patient-specific relationships between the respective signals of the electrochemical sensor and the cardiac EGM during a first period of time. Based on the patient-specific relationships, the system may estimate concentrations of the one or more analytes corresponding to the respective signals based on the cardiac EGM of the patient collected over a second period of time.
    Type: Application
    Filed: April 3, 2024
    Publication date: August 15, 2024
    Inventors: Daniel Hahn, Akhil Srinivasan, Patrick W. Kinzie, Randal C. Schulhauser, Jennifer L. Marckmann, Mohsen Askarinya, James K. Carney, David L. Probst, Santhisagar Vaddiraju, Alejo Chavez Gaxiola, Richard J. O'Brien, Anna M. Tycon, Omid Mahdavi, Shawn C. Kelley, David A. Anderson
  • Publication number: 20240273982
    Abstract: An apparatus for alerting individuals experiencing sensory limitations and/or sensory interference is provided according to the invention. The apparatus includes a user interface device and an alerting device. The user interface device includes a transceiver, a program and a reporting application. The alerting unit is in wireless communication with said transceiver of said user interface device. The alerting unit comprises a transceiver for wirelessly communicating with said user interface device; a central processing unit for receiving and processing communications from said transceiver; an alert notification device coupled to said central processing unit, said alert notification device configured to provide an alert to a user upon receipt of an alert signal from said central processing unit; and a power supply for providing power to the central processing unit, transceiver and alert notification device of the alerting unit.
    Type: Application
    Filed: June 30, 2022
    Publication date: August 15, 2024
    Inventors: JASON GERST, ALEX ADELSON, DAN HILGERT, CHRIS OWENS, ALEX ANDERSON, DAVID ECKERSON, TODD SMITH
  • Publication number: 20240271680
    Abstract: A head unit system for controlling motion of an object includes a shear thickening fluid (STF) and a chamber configured to contain a portion of the STF. The chamber further includes a front channel and a back channel. The head unit system further includes a piston housed at least partially radially within the piston compartment and separating the back channel and the front channel. The piston includes a first piston bypass and a second piston bypasses to control flow of the STF between opposite sides of the piston. The chamber further includes a set of fluid manipulation emitters to control the flow of the STF to cause selection of one of a variety of shear rates for the STF within the chamber.
    Type: Application
    Filed: March 25, 2024
    Publication date: August 15, 2024
    Applicant: Moshun, LLC
    Inventors: Timothy John Boundy, Steven Michael Barger, Terence Michael Lydon, Richard Michael Lang, Wilfredo Gonzalez, JR., Darren Michael Boundy, Eric McHugh, David Schuda, George L. Wilson, IV, Gary W. Grube, Jason K. Resch, Mario F. DeRango, John Edward Buchalo, Richard A. Herbst, Kurt Estes, Evan Anderson
  • Publication number: 20240265062
    Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.
    Type: Application
    Filed: April 12, 2024
    Publication date: August 8, 2024
    Inventors: Arthur John Redfern, Timothy David Anderson, Kai Chirca, Chenchi Luo, Zhenhua Yu
  • Publication number: 20240264952
    Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
    Type: Application
    Filed: April 18, 2024
    Publication date: August 8, 2024
    Inventors: Naveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
  • Patent number: 12050914
    Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 30, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Raymond Michael Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad, David M. Thompson
  • Publication number: 20240245053
    Abstract: Antimicrobial compositions including at least one acid and at least one anionic surfactant are provided. In particular, food contact antimicrobial compositions including at least one acid and at least one anionic surfactant provide a no-rinse compositions efficacious against Norovirus, having acceptable use solution pH that do not require use of personal protective equipment (PPE), are surface compatible and do not leave residues on treated surfaces are provided. Methods of cleaning a surface with the compositions are also provided.
    Type: Application
    Filed: March 7, 2024
    Publication date: July 25, 2024
    Inventors: Catherine Hanson, Junzhong Li, David D. McSherry, Stacy Fawbush, Kaitlin Lake, Gerard Hinrichs, Joshua Luedtke, Richard Staub, Derrick Anderson
  • Publication number: 20240248714
    Abstract: In an embodiment, a circuit includes a data path including at least a first lane of a first width and a second lane of a second, larger, width; an execution unit to execute a first instruction on data of the first width or less using the first lane, and to execute a second instruction on data greater than the first width and less than or equal to the second width using the second lane; and a control register that stores a value indicating which of the first and second lanes to be used in instruction execution by the execution unit. The circuit is configured to, based on the value stored in the control register, power off the first lane when the execution unit executes the second instruction but not the first instruction, and power off the second lane when the execution unit executes the first instruction but not the second instruction.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 25, 2024
    Inventors: Timothy David Anderson, Duc Quang Bui
  • Patent number: D1039293
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: August 20, 2024
    Assignee: Ledge Lounger, Inc.
    Inventors: Christopher Anderson, David Bier
  • Patent number: D1039381
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 20, 2024
    Assignee: Apple Inc.
    Inventors: Arsalan Aslam, Grace Tsai, David Samuel Kumka, Molly Anderson, Clement Tissandier