Patents by Inventor David Arnold

David Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7654589
    Abstract: A latching system including a latch assembly, a cup, and a keeper plate. The latch assembly includes a base, a lever, and a catch. The lever is pivotally connected to the base and the catch is pivotally connected to the lever. The base is pivotally attached to the cup such that it rotates about an axis of rotation that is perpendicular in direction in relation to the direction of the axis of rotation of the lever relative to the base. The keeper plate includes a keeper projection. The lever can be lifted and the latch assembly rotated about the axis of rotation of the base to clear the keeper from the catch and thereby allow the opening of a first closure member relative to a second closure member.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 2, 2010
    Assignee: Southco, Inc.
    Inventors: James H. Vickers, Ian Vance White, David Arnold White, Joshua James Baker
  • Patent number: 7639258
    Abstract: Methods and apparatus, including computer program products, that implement a method for determining a winding order for a glyph associated with a font. The glyph has an outline that has an outside path. In one aspect, a method includes identifying four extrema points of the outline, each being an intersection of two vectors obtained from the outline; and for each of the points, calculating a cross product of the two vectors intersecting at the point. A positive result indicates that the outside path is wound in a first direction, and a negative result indicates that the outside path is wound in an opposite, second direction. The winding order of the outside path is determined based on the cross products calculated. In a particular implementation, the method determines that the outside path is wound counter clockwise when three or four of the results are positive.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: December 29, 2009
    Assignee: Adobe Systems Incorporated
    Inventors: Terence S. Dowling, R. David Arnold
  • Patent number: 7602390
    Abstract: Methods and apparatus, including computer program products, implementing and using techniques for rendering a glyph to make it more readable. In an implementation, a glyph associated with a font to be rendered at a size is received, and a set of initial density values is calculated to provide one density value for each of a set of device pixels to represent the glyph. An initial adjustment value is calculated for the glyph. For one or more of the device pixels in the set of device pixels, a length of an edge of the glyph that passes through the device pixel is calculated. For one or more of the device pixels, the initial density value is adjusted by a final adjustment value, the final adjustment value based upon the initial adjustment value and the length of the edge of the glyph passing through the device pixel.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 13, 2009
    Assignee: Adobe Systems Incorporated
    Inventors: R. David Arnold, Terence S. Dowling
  • Patent number: 7598955
    Abstract: Methods and apparatus implementing a technique for rendering a hinted character for display in grayscale on a grayscale output device in accordance with a hinted stem placement policy. In one embodiment, the policy is a black-edge policy, by which a hinted stem is moved so that at least one of the hinted stem edges aligns with an edge of a device cell (which corresponds to an output device pixel). In another embodiment, the policy is an unbiased-stems policy, by which a hinted stem is moved a minimum distance to have it span a minimum number of device cells.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: October 6, 2009
    Assignee: Adobe Systems Incorporated
    Inventors: Terence S. Dowling, R. David Arnold
  • Patent number: 7580039
    Abstract: Methods and apparatus, including computer program products, that implement a method for adjusting a glyph outline while rendering. In one aspect a method includes receiving a glyph to be rendered at a size; generating from the glyph an outline of line segments, each line segment having two endpoints; translating the line segments all in an outward or inward direction, each line segment being moved by a distance and then rejoining pairs of adjacent line segments by extending or trimming their endpoints until each pair of adjacent line segments join at an intersection point that is an endpoint of each the line segments of the pair; and determining an augmented scaled outline of the glyph from the translated and rejoined line segments.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: August 25, 2009
    Assignee: Adobe Systems Incorporated
    Inventors: Terence S. Dowling, R. David Arnold
  • Publication number: 20090145294
    Abstract: A diaphragm actuator for a fluid process control device comprises a housing, a diaphragm, a stem, and a plate assembly. The plate assembly includes a concave plate and a convex plate, each having inner and outer radial portions. The outer radial portions compressingly engage and retain the diaphragm. The inner radial portions are compressed together onto the stem between a shoulder of the stem and a nut threaded onto the stem. Accordingly, the concave plate forcibly engages and provides a fluid-tight seal directly with the shoulder of the stem without requiring an o-ring or any other additional sealing component. Moreover, the concave and convex plates are structurally equivalent such that the actuator may easily be switched between a biased-open configuration and a biased-closed configuration.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Inventors: Douglas P. Gethmann, Ross A. Schade, David A. Arnold
  • Publication number: 20090106526
    Abstract: Embodiments of the invention are generally related to image processing, and more specifically to register files for supporting image processing. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Inventors: David Arnold Luick, Eric Oliver Mejdrieh
  • Publication number: 20090106527
    Abstract: Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 23, 2009
    Inventors: David Arnold Luick, Eric Oliver Mejdrich, Adam James Muff
  • Publication number: 20090106525
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for image processing, and more specifically to vector units for supporting image processing is provided. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.
    Type: Application
    Filed: March 14, 2008
    Publication date: April 23, 2009
    Inventors: David Arnold LUICK, Eric Oliver MEJDRICH, Adam James Muff
  • Publication number: 20090044049
    Abstract: A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in an array. Preferably, a pipeline failure causes data to be shifted one position within the array of pipelines, to by-pass the failing pipeline, so that each pipeline has only two sources of data, a primary and an alternate. Preferably, selection logic controlling the selection between a primary and alternate source of pipeline data is integrated with other pipeline operand selection logic.
    Type: Application
    Filed: October 21, 2008
    Publication date: February 12, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: David Arnold Luick
  • Publication number: 20090037694
    Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: David Arnold Luick, Eric Oliver Mejdrich, Adam James Muff
  • Patent number: 7487330
    Abstract: In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporations
    Inventors: Erik R. Altman, Kemal Ebcioglu, Michael Karl Gschwind, David Arnold Luick
  • Publication number: 20090015589
    Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Inventors: David Arnold Luick, Eric Oliver Mejdrich, Adam James Muff
  • Publication number: 20090006753
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for accessing a processor cache is provided. The design structure comprises a processor having a processor core, a level one cache, and circuitry. The circuitry is configured to execute an access instruction in the processor's core, wherein the access instruction provides an untranslated effective address of data to be accessed by the access instruction, determine whether the processor core's level one cache includes the data corresponding to the effective address of the access instruction, wherein the effective address of the access instruction is used without address translation to determine whether the processor core's level one cache includes the data corresponding to the effective address, and provide the data for the access instruction from the level one cache if the level one cache includes the data corresponding to the effective address.
    Type: Application
    Filed: March 13, 2008
    Publication date: January 1, 2009
    Inventor: DAVID ARNOLD LUICK
  • Publication number: 20090006819
    Abstract: A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline. The method further includes determining if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline. If the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, the modified data is forwarded from the first pipeline to the second pipeline.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventor: David Arnold Luick
  • Publication number: 20090006905
    Abstract: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventor: David Arnold Luick
  • Publication number: 20090006803
    Abstract: A method and apparatus for accessing cache memory in a processor. The method includes accessing requested data in one or more level one caches of the processor using requested effective addresses of the requested data. If the one or more level one caches of the processor do not contain requested data corresponding to the requested effective addresses, the requested effective addresses are translated to real addresses. A lookaside buffer includes a corresponding entry for each cache line in each of the one or more level one caches of the processor. The corresponding entry indicates a translation from the effective addresses to the real addresses for the cache line. The translated real addresses are used to access a level two cache.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventor: David Arnold Luick
  • Publication number: 20090006036
    Abstract: The present invention related to computer architecture, and more specifically to evaluating performance of processors. A performance monitor may be placed in an L2 cache nest of a processor. The performance monitor may monitor L2 cache accesses and receive performance data from one or more processor cores over a bus coupling the processor cores with the L2 cache nest. In one embodiment the bus may include additional lines for transferring performance data from the processor cores to the performance monitor.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Applicant: International Business Machines Corporation
    Inventor: David Arnold Luick
  • Publication number: 20090006812
    Abstract: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventor: David Arnold Luick
  • Publication number: 20090006823
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.
    Type: Application
    Filed: March 21, 2008
    Publication date: January 1, 2009
    Inventor: DAVID Arnold LUICK