Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.

Abstract: The present invention related to computer architecture, and more specifically to evaluating performance of processors. A performance monitor may be placed in an L2 cache nest of a processor. The performance monitor may monitor L2 cache accesses and receive performance data from one or more processor cores over a bus coupling the processor cores with the L2 cache nest. In one embodiment the bus may include additional lines for transferring performance data from the processor cores to the performance monitor.

Abstract: A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline. The method further includes determining if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline. If the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, the modified data is forwarded from the first pipeline to the second pipeline.

Abstract: A method and apparatus for executing instructions. The method includes receiving a first load instruction and a second load instruction. The method also includes issuing the first load instruction and the second load instruction to a cascaded delayed execution pipeline unit having at least a first execution pipeline and a second execution pipeline, wherein the second execution pipeline executes an instruction in a common issue group in a delayed manner relative to another instruction in the common issue group executed in the first execution pipeline. The method also includes accessing a cache by executing the first load instruction and the second load instruction. A delay between execution of the first load instruction and the second load instruction allows the cache to complete the access with the first load instruction before beginning the access with the second load instruction.

Abstract: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.

Abstract: A method and apparatus for accessing cache memory in a processor. The method includes accessing requested data in one or more level one caches of the processor using requested effective addresses of the requested data. If the one or more level one caches of the processor do not contain requested data corresponding to the requested effective addresses, the requested effective addresses are translated to real addresses. A lookaside buffer includes a corresponding entry for each cache line in each of the one or more level one caches of the processor. The corresponding entry indicates a translation from the effective addresses to the real addresses for the cache line. The translated real addresses are used to access a level two cache.

Abstract: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.

Abstract: A method and apparatus for accessing a cache. The method includes receiving a request to access the cache. The request includes an address of requested data to be accessed. The method also includes using a first portion of the address to perform an access to a first directory for the cache and using a second portion of the address to perform an access to a second directory for the cache. Results from the access to the first directory for the cache and results from the access to the second directory for the cache are used to determine whether the cache includes the requested data to be accessed.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for accessing a processor cache is provided. The design structure comprises a processor having a processor core, a level one cache, and circuitry. The circuitry is configured to execute an access instruction in the processor's core, wherein the access instruction provides an untranslated effective address of data to be accessed by the access instruction, determine whether the processor core's level one cache includes the data corresponding to the effective address of the access instruction, wherein the effective address of the access instruction is used without address translation to determine whether the processor core's level one cache includes the data corresponding to the effective address, and provide the data for the access instruction from the level one cache if the level one cache includes the data corresponding to the effective address.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: Methods and apparatus implementing and using techniques for rendering a stroke (e.g., a line or glyph). An initial adjustment value can be calculated for the stroke, and an offset amount calculated based on the initial adjustment value, such that a minimum number of device pixels will be marked by the stroke after adjusting density values of device pixels representing the stroke. A high resolution representation of the stroke (e.g., a set of device pixels each having an initial density value) is rendered so that one or more edges of the stroke is offset from a device resolution grid by the offset amount. A length of an edge of the stroke that passes through a device pixel can be calculated, and the density value of the device pixel adjusted by a final adjustment value based on the initial adjustment value and the length of the edge of the stroke.

Abstract: The invention comprises a point and cover assembly for a row crop header including a point; a cover coupled to the point with a hinge; a latch fixed to the cover, the latch having a first spring-loaded latch pin for pinning the cover to a first row unit, a second spring loaded latch pin for pinning the cover to a second row unit, and a member coupling the two latch pins together that is operable by one hand to release both latch pins; and a point support fixed to the cover, the point support comprising an elongate member fixed at its rear end to the cover and having an adjustable point rest at its front end for supporting the point at a plurality of different heights.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: An insulated container includes a bottom and four walls connected to the bottom; a top which fits on the four walls; a portion of the top is pivotally mounted so as to be opened to provide access to the insulated container through a first opening; a portion of one of the four walls is pivotally mounted so as to be opened to provide access to the insulated container through a second opening; wherein the first and second openings are contiguous to provide a combined access area to the container that extends across both the top and the one of the four walls.

Abstract: A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the primary latch, then transferred to the secondary latch. The bit value for a first thread of execution is then written to the primary latch. When a context switch is needed (when the first thread stalls and the second thread needs to begin execution), the register file bit can perform a context switch from the first thread to the second thread in a single clock cycle. The register file bit contains a backup latch inside the register file itself so that minimal extra wire paths are needed to or from the existing register file.

Abstract: A memorabilia container includes a box-like receptacle to the memorabilia. The receptacle has opposite upstanding side walls and an upstanding rear wall joining the side walls. The side walls and the rear wall have respective upper edges. A side lid is hingedly connected to each side wall. The side lid hinges are attached to the side walls below the upper edges of the side walls so that the side wall upper edge stops the side lid from opening beyond a predetermined angle. Each side lid has an interior surface, an exterior surface, and an outer edge. The side lids close together with their outer edges abutting. A rear lid is hingedly connected to the rear wall. The rear wall hinge is attached to the rear wall below the upper edge of the rear wall, so that the rear wall upper edge stops the rear lid from opening beyond a predetermined angle. The rear lid has an interior surface and an exterior surface. The rear lid closes first, and the side lids close together over the rear lid.

Abstract: Methods and apparatus implementing and using techniques for rendering a stroke (e.g., a line or glyph). An initial adjustment value can be calculated for the stroke, and an offset amount calculated based on the initial adjustment value, such that a minimum number of device pixels will be marked by the stroke after adjusting density values of device pixels representing the stroke. A high resolution representation of the stroke (e.g., a set of device pixels each having an initial density value) is rendered so that one or more edges of the stroke is offset from a device resolution grid by the offset amount. A length of an edge of the stroke that passes through a device pixel can be calculated, and the density value of the device pixel adjusted by a final adjustment value based on the initial adjustment value and the length of the edge of the stroke.

Abstract: A seat belt retractor (10) has an actuator (14) for unlocking and locking the seat belt retractor (10). An inertial sensor (18) detects changes in vehicle acceleration and interacts with the actuator (14) to lock and unlock the seat belt retractor (10). The inertial sensor (18) has one inertial sensor mass, each mass (26, 27, 29, 30, 32, 33) has a wide portion (70) and a narrow portion (72). Preferably each inertial sensor mass (26, 27, 29, 30, 32, 33) has a high density body (31) embedded in the wide portion (70) of the elastomeric material (34). The inertial sensor mass (26, 27, 29, 36, 32, 33) has a greater density than the elastomeric material (34). Moreover, the elastomeric material (34) at least partially surrounds an exterior circumferential surface (38) of the inertial sensor mass (26, 27, 29, 30, 32, 33).

Abstract: A container includes a rigid insulated body-portion that defines a first enclosed space, a base lid adapted to be reattachably fastened to an edge of the sides that is proximal to the opening, thereby covering the opening so as to at least substantially prevent fluid communication between the first enclosed space and the area outside the container, a contents-container, a contents-container lid that is adapted to be reattachably fastened to edges of the contents container that are proximal to the opening of the contents container, thereby substantially preventing fluid communication between the second enclosed space of the contents container and the space outside the contents container, the first enclosed space including an interior portion adapted to receive the contents container and a coolant portion adapted to receive at least one coolant container.