Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency and effectiveness of communications between multiprocessor clusters. Mechanisms for improving the accuracy of information available to an interconnection controller are implemented in order to allow the interconnection controller to increase reliability and reduce latency in a multiple cluster system. Protocol extensions and link layer extensions are provided with packets to convey information between interconnection controllers of separate multiprocessor clusters.

Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for transmitting memory cancels to memory controllers in the various clusters of a multiple cluster system are provided. In one example, memory cancels are transmitted between clusters when it is determined that a memory line associated with a probe is dirty. The memory cancel directs the memory controller to no longer proceed with a data fetch from main memory. In another example, memory cancels are transmitted at a home cluster based on information in a coherence directory in order to more quickly end a data fetch.

Abstract: Methods and devices are provided for controlling lock and unlock operations within a computer system. A home cluster includes a home lock manager. The home lock manager is a master lock manager for the home cluster and for a plurality of remote clusters, the plurality of remote clusters including remote cache coherency controllers and a plurality of remote processors. Lock and unlock commands from the home lock manager are transmitted by a home cache coherency controller to the remote cache coherency controllers and forwarded to the remote processors.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, memory controller filter information is used to probe a request or remote cluster while bypassing a home cluster memory controller.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, probe filter information is used to limit the number of probe requests transmitted to request and remote clusters.

Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. A variety of techniques for managing eviction of entries in the cache coherence directory are provided.

Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. A variety of techniques for managing eviction of entries in the cache coherence directory are provided.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or a home cluster. A speculative probe associated with a particular memory line is transmitted to the remote cluster before the cache access request associated with the memory line is serialized at a home cluster. When a non-speculative probe is received at a remote cluster, the information associated with the response to the speculative probe is used to provide a response to the non-speculative probe.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or a home cluster. A speculative probe associated with a particular memory line is transmitted to the remote cluster before the cache access request associated with the memory line is serialized at a home cluster. When a non-speculative probe is received at a remote cluster, the information associated with the response to the speculative probe is used to provide a response to the non-speculative probe.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluster includes mechanisms for instructing probed remote clusters to respond to the request cluster instead of to the home cluster. The home cluster can also include mechanisms for reducing the number of probes sent to remote clusters. Techniques are also included for providing the requesting cluster with information to determine the number of responses to be transmitted to the requesting cluster as a result of the reduction in the number of probes sent at the home cluster.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluster includes mechanisms for instructing probed remote clusters to respond to the request cluster instead of to the home cluster. The home cluster can also include mechanisms for reducing the number of probes sent to remote clusters. Techniques are also included for providing the requesting cluster with information to determine the number of responses to be transmitted to the requesting cluster as a result of the reduction in the number of probes sent at the home cluster.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing at a first cluster can be performed to improve overall transaction efficiency. Intervening requests from a second cluster can be handled using information from the speculative probe at the first cluster.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing can be performed before forwarding a data access request to a second cluster. The cache coherence controller can also forward the data access request to the second cluster before receiving a probe response.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing can be performed before forwarding a data access request to a second cluster. The cache coherence controller can send the data access request to the second cluster if the data access request can not be completed locally.