Abstract: A system, method and computer program product are provided for a hardware implementation of a blending of “skinning,” during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values are received. Also received is vertex data to be processed. A sum of a plurality of products may then be calculated by the multiplication of the vertex data, one of the matrices, and at least of the weights. Such sum of products is then outputted for additional processing.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for receiving vertex data. The transform module serves to transform the vertex data from a first space to a second space. Further, the transform module of the graphics pipeline system is capable of carrying out a blending operation. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. During use, the lighting module of the graphics pipeline system is capable of carrying out a fog operation.

Abstract: A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.

Abstract: A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data.

Abstract: A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.

Abstract: A graphics accelerator pipeline including a combiner stage capable of producing output values during each clock interval of the pipeline which map a plurality of textures to a single pixel or an individual texture to two pixels.

Abstract: The multiplier which includes built-in adjustments to improve circuit performance. More specifically, the multiplier is a compensated multiplier to increase the accuracy and precision of computation using analog very large scale integrated (VLSI) circuits and consists of adjustable parameters which allow for the improvement of the linear range of behavior as well as the cancellation of input offsets. A differential multiplier is further described in which adjustable parameters in addition to the four inputs to the multiplier compensate for offsets and non-linearities to result in a highly accurate analog multiplier.

Abstract: A method and apparatus for implementing intelligent priority functions at individual switching apparatus devices which comprise switching networks. The intelligent switching functions are capable of operating in real time systems with high efficiency. The switching apparatus has the capability at each stage of the network to make and/or break connections on a priority basis. If a connection is requested at a switch stage and the connection is being used by a lower priority device, the low priority connection is interrupted (broken) and the requested higher priority connection is established. After the high priority connection has completed its usage of the connection, the high priority connection is broken and the lower priority connection is re-established.

Abstract: A circuit and method for executing real time constraint solution permits real time control of computational tasks using analog very large scale integrated (VLSI) circuits. The constraints of a computation or task are first defined as a function or set of functions. The function(s) are used to produce an error measure function which described how well the constraint(s) is/are stisfied. Analog gradient descent techniques are then used to minimize the error measure function and produce an improved output of the task and optionally adjust the performance of the task. As this is performed in analog VLSI, the constraint solution can be performed continuously and continually in real time, without the limitations of discrete optimization as implemented using digital processing.

Abstract: The circuit generates an output value of an N-dimensional basis function. The circuit includes a string of sub-circuits, each sub-circuit computing a one-dimensional basis function. Each lower dimension sub-circuit is coupled to the adjacent higher dimension circuit, such that the current output is utilized as the input bias current to the adjacent higher dimension circuit. The coupling of sub-circuits in this manner provides the computation of the product of the 1-dimension basis functions produced by each of the sub-circuits.

Abstract: A circuit and method for estimating gradients of a target function using noise injection and correlation is provided. In one embodiment, an input signal is combined with an input noise signal and the combined signal is input to a circuit which computes the output of the target function. An amplified noise signal and output signal of the target function are input to a multiplier which performs a correlation of the inputs. The output of the multiplier is processed by a low-pass filter which generates the gradient. The circuit and method can be expanded to N-dimensions. Furthermore, in a alternate embodiment, a differentiator is coupled between the multiplier and amplifier and the multiplier and the output of the target function to differentiate the two signals prior to input to the multiplier. In other embodiments, the circuit may be used to compute gradient-like signals, wherein each component of the gradient is individually scaled by a different value.

Abstract: A system for quadratic and higher order interpolation of pixel color and other pixel values into a bitmap image enables enhanced shading for generation of realistic computer graphics images. The system incorporates modules for executing incremental evaluation of pixel values, utilizing forward differencing in N arbitrary directions of incremental evaluation. The system alternatively incorporates non-incremental evaluation elements for directly evaluating polynomials or executing a spline function of control points.

Abstract: Texture mapping apparatus includes a memory for storing input texture values, interpolators for generating illumination values for sets of display pixels, elements for addressing the memory to generate output texture values, and logic elements for combining the output texture values and the illumination values to generate display color values for each pixel.

Abstract: A fluid pressure reproducing relay is described having a high order of accuracy in matching the output pressure to the loading pressure under steady state conditions, having a large flow capacity for both supply and exhaust and which is small in size for its capacity, the relay having a resilient rolling seal with a vented seating arrangement that requires no clamping, having a stabilizing mass loosely attached to a force balance diaphragm assembly and in which a balanced area supply plunger is employed.