Patents by Inventor David B. Slater

David B. Slater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7592634
    Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: September 22, 2009
    Assignee: Cree, Inc.
    Inventors: Yifeng Wu, Gerald H. Negley, David B. Slater, Jr., Valeri F. Tsvetkov, Alexander Suvorov
  • Publication number: 20090166658
    Abstract: A light emitting diode includes a diode region having a gallium nitride based n-type layer, an active region and a gallium nitride based p-type layer. A first reflector layer is provided on the gallium nitride based p-type layer, and a second reflector layer is provided on the gallium nitride based n-type layer. Bonding layers, a mounting support, a wire bond and/or transparent oxide layers also may be provided.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 2, 2009
    Inventors: David B. Slater, JR., Robert C. Glass, Charles M. Swoboda, Bernd Keller, James Ibbetson, Brian Thibeault, Eric J. Tarsa
  • Publication number: 20080258161
    Abstract: A light emitting diode is disclosed that includes an active structure formed of at least p-type and n-type epitaxial layers of Group III nitride on a conductive carrier substrate. A conductive bonding system joins the active structure to the conductive carrier substrate. A first transparent ohmic contact is on the active structure adjacent the conductive carrier substrate, a second transparent ohmic contact is on the active structure opposite the conductive carrier substrate, and a third ohmic contact is on the conductive carrier substrate opposite from the active structure.
    Type: Application
    Filed: April 20, 2007
    Publication date: October 23, 2008
    Inventors: John A. Edmond, David B. Slater, Michael J. Bergmann
  • Publication number: 20080224157
    Abstract: An optoelectronic device includes a passivation layer of a dielectric material having a graded composition that varies with depth, whether continuous or stepwise, to provide a first index of refraction proximate to a semiconductor or conductor material and provide a second index of refraction adjacent to a surrounding material, such as an encapsulant. The resulting graded dielectric layer reduces Fresnel losses by reducing index of refraction mismatches between the adjacent semiconductor or conductor layer and the surrounding medium. Methods for forming graded dielectric layers include supplying a nitrogen-containing source gas at a declining flow rate or concentration, while supplying an oxygen-containing source gas an rising flow rate or concentration, to a deposition chamber.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Inventor: David B. Slater
  • Publication number: 20080217635
    Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: David Todd Emerson, Kevin Haberern, Michael John Bergmann, David B. Slater, Matthew Donofrio, John Edmond
  • Publication number: 20080210971
    Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.
    Type: Application
    Filed: August 23, 2007
    Publication date: September 4, 2008
    Inventors: Matthew Donofrio, David B. Slater, John A. Edmond, Hua-Shuang Kong
  • Patent number: 7420222
    Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: September 2, 2008
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Robert C. Glass, Charles M. Swoboda, Bernd Keller, James Ibbetson, Brian Thibeault, Eric J. Tarsa
  • Publication number: 20080083930
    Abstract: A light emitting diode is disclosed that includes a growth substrate, a substantially transparent ohmic contact on a first surface of the growth substrate, a Group III nitride, light-emitting active region on a second surface of the growth substrate, a p-type Group III nitride contact layer on the active region that transmits light generated in the active region, and a substantially transparent ohmic contact on the p-type contact layer.
    Type: Application
    Filed: April 20, 2007
    Publication date: April 10, 2008
    Inventors: John A. Edmond, David B. Slater, Michael J. Bergmann
  • Publication number: 20080073665
    Abstract: A semiconductor structure and a bonding method are disclosed that includes a device wafer, a substrate wafer, and a metal bonding system between the device wafer and the substrate wafer. The metal bonding system includes gold, tin, and nickel, and includes at least one discrete layer of gold and tin that is at least about 88 percent gold by weight.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 27, 2008
    Inventors: David B. Slater, John A. Edmond, Hua-Shuang Kong
  • Patent number: 7341175
    Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: March 11, 2008
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Patent number: 7338822
    Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: March 4, 2008
    Assignee: Cree, Inc.
    Inventors: Yifeng Wu, Gerald H. Negley, David B. Slater, Jr., Valeri F. Tsvetkov, Alexander Suvorov
  • Publication number: 20080003777
    Abstract: A semiconductor wafer, substrate, and bonding structure is disclosed that includes a device wafer that includes, for example, a plurality of light emitting diodes, a contact metal layer (or layers) on one side of the device wafer opposite the light emitting diodes, and a bonding metal system on the contact metal layer that predominates by weight in nickel and tin.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: David B. Slater, John A. Edmond, Hua-Shuang Kong
  • Patent number: 7297561
    Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: November 20, 2007
    Assignee: Cree, Inc.
    Inventors: Ralph C. Tuttle, Christopher Sean Plunket, David B. Slater, Jr., Gerald H. Negley, Thomas P. Schneider
  • Patent number: 7291529
    Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: November 6, 2007
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Matthew Donofrio
  • Patent number: 7259033
    Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 21, 2007
    Assignees: Cree, Inc., Cree Microwave, LLC
    Inventors: David B. Slater, Jr., Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Patent number: 7211833
    Abstract: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: May 1, 2007
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Bradley E. Williams, Peter S. Andrews, John A. Edmond, Scott T. Allen
  • Patent number: 7147739
    Abstract: A component assembly system is provided that includes a longitudinally elongated tape carrier, a longitudinally elongated submount carrier, and an assembly machine. A plurality of components may be attached to the tape carrier. The assembly machine is adapted to receiving the tape carrier, with the components attached thereto, and to receive the submount carrier. The assembly machine is further adapted to bring the tape carrier in close proximity to the submount carrier, and to attach the components to the submounts on the submount carrier.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: December 12, 2006
    Assignee: Cree Inc.
    Inventors: Norbert Hiller, Peter S. Andrews, David B. Slater, Jr., Gerald H. Negley
  • Patent number: 7037742
    Abstract: Light emitting diodes include a substrate, an epitaxial region on the substrate that includes therein a diode region and a multilayer conductive stack on the epitaxial region opposite the substrate. A passivation layer extends at least partially on the multilayer conductive stack opposite the epitaxial region, to define a bonding region on the multilayer conductive stack opposite the epitaxial region. The passivation layer also extends across the multilayer conductive stack, across the epitaxial region and onto the substrate. The multilayer conductive stack can include an ohmic layer on the epitaxial region opposite the substrate, a reflector layer on the ohmic layer opposite the epitaxial region and a tin barrier layer on the reflector layer opposite the ohmic layer. An adhesion layer also may be provided on the tin barrier layer opposite the reflector layer. A bonding layer also may be provided on the adhesion layer opposite the tin barrier layer.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 2, 2006
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Bradley E. Williams, Peter S. Andrews
  • Patent number: 7034328
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: April 25, 2006
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.
  • Patent number: 7026659
    Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region. The first face of the substrate may include therein a plurality of grooves that define the plurality of triangular pedestals in the substrate. The grooves may include tapered sidewalls and/or a beveled floor.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: April 11, 2006
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Robert C. Glass, Charles M. Swoboda, Bernd Keller, James Ibbetson, Brian Thibeault, Eric J. Tarsa