Abstract: Reflective ohmic contacts for n-type silicon carbide include a layer consisting essentially of nickel on the silicon carbide. The layer consisting essentially of nickel is configured to provide an ohmic contact to the silicon carbide, and to allow transmission therethrough of optical radiation that emerges from the silicon carbide. A reflector layer is on the layer consisting essentially of nickel, opposite the silicon carbide. A barrier layer is on the reflector layer opposite the layer consisting essentially of nickel, and a bonding layer is on the barrier layer opposite the reflector layer. It has been found that the layer consisting essentially of nickel and the reflector layer thereon can provide a reflective ohmic contact for silicon carbide that can have low ohmic losses and/or high reflectivity.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: Methods of forming a light emitting diode are provided by scoring a semiconductor substrate having a light emitting region formed thereon so as to provide score lines between individual ones of a plurality of light emitting diodes. The semiconductor substrate is then broken along selected ones of the score lines so as to provide a unitized subset of the plurality of light emitting diodes. The unitized subset includes at least two light emitting diodes. Electrical connections are provided to the light emitting diodes of the unitized subset of the plurality of light emitting diodes. The score lines may also define the individual ones of the light emitting diodes.

Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.

Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.

Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.

Abstract: Light emitting diodes include a substrate, an epitaxial region on the substrate that includes therein a diode region and a multilayer conductive stack on the epitaxial region opposite the substrate. A passivation layer extends at least partially on the multilayer conductive stack opposite the epitaxial region, to define a bonding region on the multilayer conductive stack opposite the epitaxial region. The passivation layer also extends across the multilayer conductive stack, across the epitaxial region and onto the substrate. The multilayer conductive stack can include an ohmic layer on the epitaxial region opposite the substrate, a reflector layer on the ohmic layer opposite the epitaxial region and a tin barrier layer on the reflector layer opposite the ohmic layer. An adhesion layer also may be provided on the tin barrier layer opposite the reflector layer. A bonding layer also may be provided on the adhesion layer opposite the tin barrier layer.

Abstract: A method for forming an ohmic contact to silicon carbide for a semiconductor device comprises implanting impurity atoms into a surface of a silicon carbide substrate thereby forming a layer on the silicon carbide substrate having an increased concentration of impurity atoms, annealing the implanted silicon carbide substrate, and depositing a layer of metal on the implanted surface of the silicon carbide. The metal forms an ohmic contact “as deposited” on the silicon carbide substrate without the need for a post-deposition anneal step.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region. The first face of the substrate may include therein a plurality of grooves that define the plurality of triangular pedestals in the substrate. The grooves may include tapered sidewalls and/or a beveled floor.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: A monollithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and reoxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode.

Abstract: A method is disclosed for obtaining improved oxide layers and resulting improved performance from oxide based devices. The method comprises exposing an oxide layer on a silicon carbide layer to an oxidizing source gas at a temperature below the temperature at which SiC would begin to oxidize at a significant rate, while high enough to enable the oxidizing source gas to diffuse into the oxide layer, and while avoiding any substantial additional oxidation of the silicon carbide, and for a time sufficient to densify the oxide layer and improve the interface between the oxide layer and the silicon carbide layer.

Abstract: A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like.

Abstract: A method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device. The method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinsic parasitic base resistance and the extrinsic parasitic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced. The method includes formming symmetric emitter and collector portions using front and backside processing of the wafer, respectively. The symmetric emitter and collector virtually eliminates the extrinsic collector and emitter regions of the device thereby virtually eliminating the extrinsic base-collector and base-emitter capacitance. The extrinsic base contact region may also be increased to minimize the base contact resistance without increasing parasitic capacitive elements of the device.

Abstract: A method of manufacturing heterojunction transistors having self-aligned contacts. In manufacturing a heterojunction bipolar transistor, a collector and a base layer are deposited on a substrate. A masking layer is deposited on the base layer and selectively etched to form an aperture therein, exposing the base layer. An emitter having a mesa structure is grown epitaxially on the exposed base layer to produce lateral overhang portions. The overhang portions may be formed by continuing the epitaxial growth to form lateral overgrowth portions overlapping the masking material. The masking layer is removed and self-aligned contacts are formed to the base and emitter regions using the lateral overhang portions which provide separation between the emitter structure and the contacts to the base layer.