Patents by Inventor David Blaauw
David Blaauw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028900Abstract: Recent advances in model pruning have enabled sparsity-aware deep neural network accelerators that improve the energy efficiency and performance of inference tasks. SONA, a novel transform-domain neural network accelerator is introduced in which convolution operations are replaced by element-wise multiplications and weights are orthogonally structured to be sparse. SONA employs an output stationary dataflow coupled with an energy-efficient memory organization to reduce the overhead of sparse-orthogonal transform-domain kernels that are concurrently processed while maintaining full multiply-and-accumulate (MAC) array utilization without any conflicts. Weights in SONA are non-uniformly quantized with bit-sparse canonical-signed-digit (BS-CSD) representations to reduce multiplications to simpler additions.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Hun-Seok KIM, David BLAAUW, Dennis SYLVESTER, Yu CHEN, Pierre ABILLAMA, Hyochan AN
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Publication number: 20230244746Abstract: A computer-implemented method is presented for performing a computation with a neural network. The method includes: receiving a first input patch of data; applying a Walsh-Hadamard transform to the input patch to yield a transformed input patch in a transformed domain; computing an element-wise product of the transformed input patch and a kernel of the neural network; applying an inverse Walsh-Hadamard transform to the element-wise product to yield an intermediate matrix; and creating a first output patch from the intermediate matrix, where the size of the first output patch is smaller than the intermediate matrix.Type: ApplicationFiled: February 17, 2022Publication date: August 3, 2023Inventors: Dennis SYLVESTER, David BLAAUW, Yu CHEN, Pierre ABILLAMA, Hun-Seok KIM
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Publication number: 20230146711Abstract: A motion sensing system uses high-voltage biasing to achieve high resolution with ultra-low power. The motion sensing system consists of a motion sensor, a readout circuit, and a high-voltage bias circuit to generate the optimized bias voltage for the motion sensor. By using the high-voltage bias, the signal from the motion sensor is raised above the readout circuit's noise floor, eliminating the power-hungry amplifier and signal-chopping used in conventional motion sensing systems. The bias circuit, while producing the programmable bias voltages for the motion sensor, also compensates for the process mismatch raised by the high voltage biases.Type: ApplicationFiled: November 9, 2022Publication date: May 11, 2023Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Yimai PENG, David BLAAUW, Dennis SYLVESTER, David Kyojin CHOO
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Patent number: 9716381Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.Type: GrantFiled: September 19, 2014Date of Patent: July 25, 2017Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Yen-po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, Dennis Sylvester, David Blaauw
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Patent number: 9589601Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.Type: GrantFiled: March 16, 2015Date of Patent: March 7, 2017Assignees: ARM Limited, The Regents of the University of MichiganInventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
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Publication number: 20160276000Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
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Patent number: 9147443Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.Type: GrantFiled: May 16, 2012Date of Patent: September 29, 2015Assignee: The Regents Of The University of MichiganInventors: Scott Hanson, Dennis Sylvester, David Blaauw
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Publication number: 20150085406Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.Type: ApplicationFiled: September 19, 2014Publication date: March 26, 2015Inventors: Yen-po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, Dennis Sylvester, David Blaauw
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Patent number: 8564275Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.Type: GrantFiled: June 25, 2010Date of Patent: October 22, 2013Assignee: The Regents of the University of MichiganInventors: Mingoo Seok, Dennis Sylvester, David Blaauw, Scott Hanson, Gregory Chen
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Publication number: 20120293212Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Scott Hanson, Dennis Sylvester, David Blaauw
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Publication number: 20100327842Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.Type: ApplicationFiled: June 25, 2010Publication date: December 30, 2010Applicant: The Regents of The University of MichiganInventors: Mingoo Seok, Dennis Sylvester, David Blaauw, Scott Hanson, Gregory Chen
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Publication number: 20070288798Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: ApplicationFiled: August 16, 2007Publication date: December 13, 2007Applicants: ARM Limited, University of MichiganInventors: Krisztian Flautner, Todd Austin, David Blaauw, Trevor Mudge
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Publication number: 20070162798Abstract: An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.Type: ApplicationFiled: December 11, 2006Publication date: July 12, 2007Applicants: ARM Limited, Regents of the University of MichiganInventors: Shidhartha Das, David Blaauw, David Bull
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Publication number: 20070103995Abstract: A signal interface for interfacing with an address decoder and a method of address decoding are disclosed.Type: ApplicationFiled: November 7, 2005Publication date: May 10, 2007Applicants: ARM Limited, The Regents of the University of MichiganInventors: David Blaauw, David Bull, Shidhartha Das
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Publication number: 20060253666Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: ApplicationFiled: February 14, 2006Publication date: November 9, 2006Applicants: ARM Limited, University of MichiganInventors: Krisztian Flautner, David Blaauw, Trevor Mudge, Nam Kim, Steven Martin
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Publication number: 20060200699Abstract: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.Type: ApplicationFiled: December 13, 2005Publication date: September 7, 2006Applicants: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, David Bull, Todd Austin, David Blaauw, Trevor Mudge
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Publication number: 20060018171Abstract: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.Type: ApplicationFiled: June 13, 2005Publication date: January 26, 2006Applicant: ARM LimitedInventors: Todd Austin, David Blaauw, Trevor Mudge, Dennis Sylvester, Krisztian Flautner
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Publication number: 20050246613Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: ApplicationFiled: April 21, 2005Publication date: November 3, 2005Applicants: ARM Limited, University of MichiganInventors: David Blaauw, David Bull, Shidhartha Das
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Systematic and random error detection and recovery within processing stages of an integrated circuit
Publication number: 20050022094Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: ApplicationFiled: July 23, 2004Publication date: January 27, 2005Inventors: Trevor Mudge, Todd Austin, David Blaauw, Krisztian Flautner -
Patent number: 6074429Abstract: Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).Type: GrantFiled: March 3, 1997Date of Patent: June 13, 2000Assignee: Motorola, Inc.Inventors: Satyamurthy Pullela, Stephen C. Moore, David Blaauw, Rajendran Panda, Gopalakrishnan Vijayan