Abstract: A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).

Abstract: The present invention relates to a method (100, 150, 200) and associated data processing system (250) for determining a standard cell height within an integrated circuit design. A plurality of cell types, each cell type including a plurality of cell structures are received (102). Then, weighting values are received, one for each cell type (104). Expected intercell connection densities are preferably also received. Various target cell heights are processed with the plurality of cell types, the weighting values, and the expected intercell connection densities to generate a standard cell height (106). The standard cell height used with the integrated circuit design produces an optimized integrated circuit area, preferably a minimum area. The present invention includes a method (200) and system (250) for selecting an optimized standard cell height that, when used with a place-and-route tool to generate a physical design file (204) produces an optimized physical integrated circuit design.