Patents by Inventor David C. Thomas

David C. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040142565
    Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
    Type: Application
    Filed: October 16, 2003
    Publication date: July 22, 2004
    Inventors: Edward C. Cooney, Robert M. Geffken, Vincent J. McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
  • Publication number: 20040067511
    Abstract: The present invention provides methods and kits for the rapid exponential amplification of nucleic acid molecules using a padlock probe. The present invention improves upon the existing methods for amplifying padlock probes by eliminating or delaying the appearance of artifact products that cause false positive results, and also increase the sensitivity and speed of the assay. Further provided are nucleic acid amplification primers containing non-informative base analogs.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 8, 2004
    Inventor: David C. Thomas
  • Patent number: 6674168
    Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: January 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Robert M Geffken, Vincent J McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
  • Patent number: 6340601
    Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: January 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Thomas F. Curran, Jr., Timothy C. Krywanczyk, Michael S. Lube, Matthew D. Moon, Rock Nadeau, Clark D. Reynolds, Dean A. Schaffer, Joel M. Sharrow, Paul H. Smith, Jr., David C. Thomas, Eric J. White, Kenneth H. Yao
  • Patent number: 5523253
    Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
    Type: Grant
    Filed: February 16, 1995
    Date of Patent: June 4, 1996
    Assignee: International Business Machines Corp.
    Inventors: Richard A. Gilmour, Thomas J. Hartswick, David C. Thomas, Ronald R. Uttecht, Erick G. Walton
  • Patent number: 5420455
    Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: May 30, 1995
    Assignee: International Business Machines Corp.
    Inventors: Richard A. Gilmour, Thomas J. Hartswick, David C. Thomas, Ronald R. Uttecht, Erick G. Walton
  • Patent number: 5255980
    Abstract: A temperature sensing system has a signal means which provides a signal representative of a temperature responsive luminescence, where the luminescence has a characteristic time-rate-of-decay. A means for comparison is connected to the signal means and samples the signal during two time intervals, the first interval overlapping the second. The averages of the samples are compared to provide a difference signal representative of the difference between the two measured averages. Control means coupled to the comparison means provide an output representing the temperature as a function of the time-rate-of-decay, by adjusting the overlapping intervals so that the difference signal converges to a preselected limit.
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: October 26, 1993
    Assignee: Rosemount Inc.
    Inventors: David C. Thomas, Stephen C. Jensen, Gerald R. Cucci, Charles M. Peterson, Shelle D. Tilstra, Steven J. Rychnovsky
  • Patent number: 5211480
    Abstract: A temperature sensing system has a signal means which provides a signal representative of a temperature responsive luminescence, where the luminescence has a characteristic time-rate-of-decay. A means for comparison is connected to the signal means and samples the signal during two time intervals, the first interval overlapping the second. The averages of the samples are compared to provide a difference signal representative of the difference between the two measured averages. Control means coupled to the comparison means provide an output representing the temperature as a function of the time-rate-of-decay, by adjusting the overlapping intervals so that the difference signal converges to a preselected limit.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: May 18, 1993
    Assignee: Rosemount Inc.
    Inventors: David C. Thomas, Stephen C. Jensen, Gerald R. Cucci, Charles M. Peterson, Shelle D. Tilstra, Steven J. Rychnovsky
  • Patent number: 4907066
    Abstract: A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1.times.10.sup.17 cm.sup.-2 is used. The silicon or tungsten implant allows seeding of the tungsten or other retractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: March 6, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: David C. Thomas, S. Simon Wong
  • Patent number: 4833517
    Abstract: A vertical ballistic transistor is described. Base metallic contacts of reliable thickness are deposited on a carrier depletable layer and diffuse into the base. A depletion region forms in the depletable layer. The depletion region electrically isolates the base contact from the emitter. The thickness of the depletable layer prevents the generation of usual depletion regions in the base that tend to cut off base current.
    Type: Grant
    Filed: April 27, 1987
    Date of Patent: May 23, 1989
    Assignee: International Business Machines Corporation
    Inventors: Mordehai Heiblum, Christina M. Knoedler, David C. Thomas
  • Patent number: 4746621
    Abstract: A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1.times.10.sup.17 cm.sup.-2 is used. The silicon or tungsten implant allows seeding of the tungsten or other refractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects.
    Type: Grant
    Filed: December 5, 1986
    Date of Patent: May 24, 1988
    Assignee: Cornell Research Foundation, Inc.
    Inventors: David C. Thomas, S. Simon Wong
  • Patent number: 4654792
    Abstract: A data processing system includes means for verifying the authority of data-entry devices to input data and the authenticity of such data. The system includes a central data-processing computer, a plurality of data-entry devices connected to the central computer for providing input data, a central security system, connected to the central computer for identifying the data-entry devices and verifying that such devices are authorized to input data, and a programmable external security device connected to at least one of said authorized data-entry devices. The external security device is programmed by the central security system to exchange user-identifier and user transaction-related data with this data-entry device and with the central security system.
    Type: Grant
    Filed: April 30, 1984
    Date of Patent: March 31, 1987
    Assignee: Corban International, Ltd.
    Inventor: David C. Thomas
  • Patent number: 4650369
    Abstract: A low headroom culvert is provided wherein a series of shallow arch-shaped flat metallic sections are overlappingly secured together. Torsion and buckle resistant reinforcing cross ribbing elements are affixed to the exterior culvert sections at selected points along the culvert to form girder-like beams. The improved culvert structure provides reduced hydraulic flow resistance, can be easily installed and requires less metal for its manufacture in comparison to culverts made of corrugated sheet.
    Type: Grant
    Filed: November 27, 1985
    Date of Patent: March 17, 1987
    Assignee: Kaiser Aluminum & Chemical Corporation
    Inventors: David C. Thomas, John W. Alcorn, William T. Nearn, II
  • Patent number: 4446519
    Abstract: Security for computer software is achieved by providing each purchaser of a software package with an electronic security device which must be operatively connected to the purchaser's computer. The software sends coded interrogation signals to the electronic security device which processes the interrogation signals and transmits coded response signals to the software. The program will not be executed unless the software recognizes the response signals according to preselected security criteria.
    Type: Grant
    Filed: May 26, 1981
    Date of Patent: May 1, 1984
    Assignee: Corban International, Ltd.
    Inventor: David C. Thomas
  • Patent number: 4423781
    Abstract: Specification discloses a process for completing a wellbore into a subterranean reservoir. In completing the wellbore, a completion fluid is pumped into the wellbore casing to displace the mud contained therein, the improvement comprising pumping a spacer system into the wellbore casing before pumping the completion fluid into the wellbore. The spacer system comprises a spacer fluid having a viscosity sufficiently high such that the spacer fluid exists in either laminar or plug flow at normal circulation rates.
    Type: Grant
    Filed: May 3, 1982
    Date of Patent: January 3, 1984
    Assignee: Standard Oil Company
    Inventor: David C. Thomas
  • Patent number: 4094810
    Abstract: An improved process for providing an aqueous slurry of an ash concentrate composition wherein predetermined amounts of the composition are mixed into a solution of water and a surfactant at a predetermined rate. The slurry is pumpable and is produced via the process of the present invention without the necessity of providing pH adjustments.
    Type: Grant
    Filed: June 1, 1976
    Date of Patent: June 13, 1978
    Assignee: Kerr-McGee Corporation
    Inventor: David C. Thomas
  • Patent number: 4046023
    Abstract: A transmission, in which power is transmitted from one variable diameter pulley to another through an endless band, has an automatic band tensioning mechanism. The band tensioning mechanism includes a tensioning shaft, an adjusting wheel rotatably mounted on the shaft, and a spring connected between the shaft and the wheel. A worm engaged with the wheel is mounted on a shaft slidably received in a locking member. The worm has a locking shoulder at one end which is normally urged, by the spring acting through the wheel, into engagement with a locking shoulder on one end of the locking member. The worm is moved out of locking engagement against the bias of the spring for rotation of the worm and wheel, and tightening of the spring.
    Type: Grant
    Filed: October 1, 1976
    Date of Patent: September 6, 1977
    Assignee: FMC Corporation
    Inventors: Richard G. Henle, Clifton S. Merkert, David C. Thomas