Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.

Abstract: A power switching device (e.g., a power MOSFET) drives relatively large surges of pulsed power through a laser emitter of a Time of Flight (TOF) determining system where both the power switching device and laser emitter are closely packed on a printed circuit board having further closely packed and temperature sensitive other components. Waveforms of pulse trains that control the power switching device are programmably defined and thus may include pulse durations that are unduly large or spacing between pulses that are unduly small such that overheating may occur. A pulse duration limiting circuit is provided having an analog integrator configured to integrate over time, the programmably defined pulses and a voltage triggered clamping device coupled to an output of the analog integrator. The voltage triggered clamping device has a predetermined threshold voltage at and above which it is switched from a relatively low transconductances mode to a substantially higher transconductances mode.

Abstract: A power supply is configured to automatically and rapidly switch from a voltage maintaining mode to a current limiting mode (at times that are unpredictable from a point of view of the power supply) when supplying replenishing current to a combination of a power insulated gate switching device and power capacitor that drive relatively large surges of pulsed power through a load such as a laser emitter of a Time of Flight (TOF) determining system. The current limiting mode is automatically activated by the start of each train of large surges of pulsed power and it replenishes charge to the power capacitor on a time averaged basis such that the capacitor develops a temperature appropriate voltage for providing the time averaged current to the power insulated gate switching device and its load and causing the load (e.g., laser) to output a desired amount of output power.

Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.

Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.

Abstract: A power supply is configured to automatically and rapidly switch from a voltage maintaining mode to a current limiting mode (at times that are unpredictable from a point of view of the power supply) when supplying replenishing current to a combination of a power insulated gate switching device and power capacitor that drive relatively large surges of pulsed power through a load such as a laser emitter of a Time of Flight (TOF) determining system. The current limiting mode is automatically activated by the start of each train of large surges of pulsed power and it replenishes charge to the power capacitor on a time averaged basis such that the capacitor develops a temperature appropriate voltage for providing the time averaged current to the power insulated gate switching device and its load and causing the load (e.g., laser) to output a desired amount of output power.

Abstract: A power switching device (e.g., a power MOSFET) drives relatively large surges of pulsed power through a laser emitter of a Time of Flight (TOF) determining system where both the power switching device and laser emitter are closely packed on a printed circuit board having further closely packed and temperature sensitive other components. Waveforms of pulse trains that control the power switching device are programmably defined and thus may include pulse durations that are unduly large or spacing between pulses that are unduly small such that overheating may occur. A pulse duration limiting circuit is provided having an analog integrator configured to integrate over time, the programmably defined pulses and a voltage triggered clamping device coupled to an output of the analog integrator. The voltage triggered clamping device has a predetermined threshold voltage at and above which it is switched from a relatively low transconductances mode to a substantially higher transconductances mode.

Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.

Abstract: Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of floating point inputs and exponent logic coupled to the mantissa logic. The exponent logic adjusts the combination of an exponent portion of the floating point inputs by a predetermined value to produce a shift amount and allows pipeline stages in the mantissa logic, wherein an unnormalized floating point result is produced from the mantissa logic on each clock cycle.

Abstract: Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.

Abstract: A Bus Analyzer Unit (BAU) for performing trace analysis on either or both the global bus (GBus) or the I/O bus of a semiconductor chip. The BAU has a GBus trace unit and an I/O bus trace unit, each with its own trace logic. Each unit has filters and comparators which determine what data is recorded and when it is recorded. Trace data recorded by the units is written to a programmable, circular trace buffer in local memory or an SDRAM. Each trace unit has two registers holding the start and end addresses of the trace buffer. Each unit has a next address register containing the next address to which data may be written. As data is written, the next address register is incremented. When the next address register equals the value in the end address register, the next address register is reloaded with the address in the start register.

Abstract: Disclosed is a multiprocessor system including a semaphore register and a semaphore interrupt register. In addition, for each processor in the multiprocessor system, there is a semaphore interrupt enable register. If a first processor finds that a semaphore cell of the semaphore register holds a “1” indicating that an associated shared resource is being accessed by a second processor, the first processor sets a corresponding semaphore interrupt enable cell of the semaphore interrupt enable register to “1” so as to enable semaphore interrupt. When the second processor finishes with the shared resource, the second processor writes a 0 into the semaphore cell, causing a corresponding semaphore interrupt cell of the semaphore interrupt register to hold a “1”. This, combined with the fact that the semaphore interrupt enable cell also holds a “1”, causes an interrupt to the first processor. In response, the first processor services the interrupt and accesses the shared resource.

Abstract: An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.

Abstract: Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies.

Abstract: A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

Abstract: A system and method for finding available memory space associated with an inactive memory transfer controller and activating the inactive memory transfer controller using indexed addressing. A memory transfer engine includes a plurality of memory transfer controllers, each configured to move data from a source address to a destination address. An active memory transfer controller can execute an instruction to find an inactive memory transfer controller associated with available memory space. The inactive memory transfer controller is activated by writing to its hardware registers, thereby assigning it a task, using indexed addressing.

Abstract: Methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. The first mechanism, Parameter List Pointer (PLP) FIFO Wake Up, wakes up an MTC after an external agent writes to an MTC's PLP FIFO. This activates the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events; wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event. The second mechanism wakes up an MTC after an external agent writes to an MTC's external wake-up address. This sets the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This approach only recognizes one event and one source. Events may not be queued using this approach.

Abstract: An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device on the bus. The master and target devices connect to the bus via a global bus interface with FIFO registers acting as buffers, and the target interface includes a TACK generator that flips the state of the global bus' TACK line upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) generates a TACK signal when no device is on the bus, and also detects the absence of any TACK response by monitoring the state of the TACK line, thereby indicating that a master device bus attempted to address a nonexistent target a device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.

Abstract: A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

Abstract: Disclosed is a voltage translation circuit 400 that can translate different voltage levels (transmit logics between circuits operating at different voltage levels) faster but consumes less energy than that of prior art. The voltage translation circuit 400 of the present invention utilizes two transistors (transmission NMOS transistor 160 and transmission PMOS transistor 200) in parallel and in combination with a bootstrap circuit 195 consisting of a pull-up control CMOS inverter 170, 180 and a pull-up PMOS transistor 190. When node 140 rises from 0V to 3V (LVDD, i.e. logic 1), transmission PMOS transistor 200 helps to raise the input voltage to pull-up control CMOS inverter 170, 180 faster and therefore helps to turn on pull-up PMOS transistor 190 faster and hence raise the voltage of node 155 faster. This in turn helps turn off PMOS transistor 170 sooner, and hence stop the transition current going through transistors 170 and 180 sooner.