Abstract: Disclosed is a computer system and method for communications between devices in the computer system. The computer system comprises a global bus which includes a Transfer Acknowledge (TACK) wire and two Command Reject (CRJ) wires for notifying a master device of different situations after the master device sends a command or data octet (64 bits) to a target device. If the target device receives the octet, it toggles the TACK line. After that, if the target device accepts the command octet, it sends 00 on the two CRJ lines. But if it rejects the octet, it sends 01, 10, or 11 on the two CRJ lines indicating to the master device how long the master should wait before resending the octet. If the command octet is sent to a nonexistent target device, the TACK line does not toggle. The master recognizes this situation and acts accordingly.

Abstract: Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies.

Abstract: Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.

Abstract: A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain operation codes multiple meanings. For most operations, the register codes refer to general purpose registers as such. However, for certain operations, including move and add, register codes 30 and 31 in the source register code field of the instruction word indicate that the next instruction word contains immediate data for that operation instead of the operand being located in the specified register itself. Further, for load, store and jump operations, the source register codes 30 and 31 in the source register code field indicates that those registers are to be used as base or index registers for indexed addressing, with an offset in the following instruction word added to the general purpose register 30 or 31 contents to form the address.

Abstract: A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

Abstract: A fast switching, device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

Abstract: An integrated circuit fast transmission switching device is provided which comprises a first input/output lead having a bus capacitance Cb; a second input/output lead having a bus capacitance Cb; a first bidirectional field-effect transistor having an internal resistance Ri and an internal capacitance Ci including a first input/output terminal and a second input/output terminal and a gate terminal, said first terminal being connected to said first lead and said second terminal being connected to said second lead, so as to pass bidirectional external data signals between said first and second leads when said transistor is turned on and so as to block the passage of external data signals between said first and second leads when said transistor is turned off; wherein Ri and Ci for the field-effect transistor are such that Ri(Ci+Cb) is less than 6.

Abstract: Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pinsetting device for each lane, a pinsetter control unit, a game control unit, a bowler input station and a pair of overhead display monitors. The game control unit is operable under the control of a game control program stored in a memory for automatically operating the pinsetter control units during game play to selectively set a sequence of pin patterns on the lane, which patterns may comprise any array of pins. The game control unit responsive to pin fall data received from the gamesetter generates scoring information which is displayed using video graphic displays on the overhead monitors. The game control program can be any one of a plurality of different game programs which may be downloaded to the memory from a memory associated with the manager's control terminal.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pinsetting device for each lane, a pinsetter control unit, a game control unit, a bowler input station and a pair of overhead display monitors. The game control unit is operable under the control of a game control program stored in a memory for automatically operating the pinsetter control units during game play to selectively set a sequence of pin patterns on the lane, which patterns may comprise any array of pins. The game control unit responsive to pin fall data received from the gamesetter generates scoring information which is displayed using video graphic displays on the overhead monitors. The game control program can be any one of a plurality of different game programs which may be downloaded to the memory from a memory associated with the manager's control terminal.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pinsetting device for each lane, a pinsetter control unit, a game control unit, a bowler input station and a pair of overhead display monitors. The game control unit is operable under the control of a game control program stored in a memory for automatically operating the pinsetter control units during game play to selectively set a sequence of pin patterns on the lane, which patterns may comprise any array of pins. The game control unit responsive to pin fall data received from the gamesetter generates scoring information which is displayed using video graphic displays on the overhead monitors. The game control program can be any one of a plurality of different game programs which may be downloaded to the memory from a memory associated with the manager's control terminal.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pinsetting device for each lane, a pinsetter control unit, a game control unit, a bowler input station and a pair of overhead display monitors. The game control unit is operable under the control of a game control program stored in a memory for automatically operating the pinsetter control units during game play to selectively set a sequence of pin patterns on the lane, which patterns may comprise any array of pins. The game control unit responsive to pin fall data received from the gamesetter generates scoring information which is displayed using video graphic displays on the overhead monitors. The game control program can be any one of a plurality of different game programs which may be downloaded to the memory from a memory associated with the manager's control terminal.

Abstract: A bowling center system includes a plurality of bowling lanes and a plurality of bowling scoring systems each connected to a manager's control system. A video distribution system includes a memory device for storing data representing a plurality of video segments and generating video signals. A plurality of video display terminals are remotely located from the manager's control system and are operable to display video information responsive to a received video signal. A video communication network connects to the memory device and the display terminals. The manager's control system responds to a selection for a particular video segment to transmit a video signal to convey video segment information responsive to data read from the memory device to a selected one of the video display terminals.

Abstract: Apparatus and a method for easily expanding the effective width of the data words of a CAM without significantly increasing the basic width of the data storage registers or comparand register. A plurality of comparison blocks each include a register for data words having a predetermined width. Each data word includes a start bit, which indicates that a data word is the first data word of a much larger data word (or data line), and a chain bit, which indicates that a match has occurred between part of a comparand and the data word stored in the register. A maskable comparator provides a match output signal. The start bit is initially loaded into the chain-bit register for a data word. A latch is provided for storing the value of the chain bit from a preceding register into the chain-bit register of a following register. A priority encoder receives the match output signals from each of the comparators of the comparison blocks to identify the highest-priority comparison block, and the corresponding data line.

Abstract: A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

Abstract: A high speed dual-port burst access memory (BAM) is disclosed that is capable of operating in both a burst access mode and random access mode simultaneously. The architecture of the high speed BAM permits random or burst access read or write operations on one port while simultaneously supporting sequential reading or writing in a burst or random mode of operation on a second port. Burst access can also be stopped and restarted for any number of clock cycles independently at each port. The BAM can also be configured as a high speed FIFO.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pin setting device for each lane, a pin setter control unit, a game scoring control unit, a bowler input station and a pair of overhead display monitors. A manager's control system provides accounting control over the bowling center system and is operable to communicate with a selected game control unit as necessary. A plurality of remote terminals are provided associated with selected ones of the lane pair control systems. Each remote terminal system includes a keyboard and a display monitor. The remote terminal operates under the control of the game unit to allow a user thereof to enter requests for video displays. The video displays include, the example, ball trajectory displays which illustrate the path of the ball in the bowling lane, or dynamic displays, such as for training, generated by video source devices associated with the manager's control system.

Abstract: A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

Abstract: A bowling center system includes a plurality of lane pair control systems each including a pin setting device for each lane, a pin setter control unit, a game control unit, a bowler input station and a pair of overhead display monitors. The game control unit is operable under the control of a game control program stored in a memory for automatically operating the pin setter control units during game play to selectively set a sequence of pin patterns on the lane. A manager's control system is coupled to each of the lane pair control systems and includes a bowler input station similar to the game control unit bowler input station.

Abstract: To provide a means for the safe, premature, abortion of a write cycle without additional, read cycle, pipeline delays multiplexers and registers are included configured to store the address and data signals externally developed during a write cycle and to store in a RAM array the stored data at the stored address during the next write cycle. A comparator is included, configured to compare each stored address with each current address. Also included is a multiplexer configured to, during a read cycle, provide from the RAM array the currently addressed data when the current address is different than the stored address and to, during a read cycle, provide the register stored data when the current address matches the stored address.