Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

Abstract: A test mode of a memory device may be invoked that varies the sense amplifier clocking of the memory device as a function of manipulation of a control signal external to the memory device. At the appropriate logic state of a test mode enable signal, the test mode of the memory device is entered. Normal clocking of the sense amplifier is suspended during the test mode and the sense amplifier is clocked according to the transition of an external control signal from a first logic state to a second logic state. A predetermined period of time after the transition of the external control signal, the sense amplifier if clocked.

Abstract: A memory structure features a write driver circuit that is controlled to assist equilibrate devices recover one or more bitlines attached to a memory cell following the completion of a write operation of the memory cell. After the write operation, a write bus true and a write bus complement generated by the write driver are coupled to bitlines and equilibration devices by passgates controlled by a control signal.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

Abstract: Therefore, according to the present invention, one or more bond pads of a memory device are connected to a corresponding address buffer or address buffers by a selection circuit which selectively allows the address buffer to ignore a signal on the bond pad. In order to define a smaller density memory device, the signal on the bond pad is ignored, and the selection circuit internally forces a logic state on the address buffer which points to the desired smaller density memory device. The memory devices and the smaller density memory devices are packaged and bonded identically and then sorted and branded such that it is not necessary to use the double inking technique. The present invention may be applied to a plurality of bond pads and corresponding address buffers. According to a preferred embodiment of the invention, the selection circuit has of a plurality of fuses which may be selectively blown to cause the address buffer to ignore a signal on the bond pad.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.

Abstract: Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memory cells. All active devices in the memory device are turned off or limited to linear region operation. This allows a supervoltage to be applied to the wordlines with internal nodes of the memory cells held low by the bitlines, stressing an oxide barrier between memory cells and wordlines without damaging active devices due to the supervoltage.

Abstract: The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track changes in a power supply voltage relative to a voltage at the input pad. The circuit is connected in series between the input pad and the input the input buffer.

Abstract: An output driver circuit an integrated circuit memory device prevents crowbar currents from occurring. The output driver uses just one resistive element having multiple taps so that the amount of silicon area used for slew rate control is minimized. The signals which control the output driver devices are carefully balanced for no skew and cross at a voltage level of Vcc/2 so that there is no crowbar current generated during tri-stating of the output driver output signal.

Abstract: According to the present invention, the data access time of a chip select condition of a synchronized memory integrated circuit device is pipelined so that it approximates the normal access time of data for the device. The response time to the chip enable signal during a deselect condition is immediate and thus is not pipelined. The access time of data due to a chip select condition is pipelined and matched with the normal access time of data propagation so that any access time pushout previously incurred when transitioning the device output signal from a high impedance (disabled) to a low impedance (enabled) state is eliminated. The circuitry of the present invention tri-states the output pin of the synchronized memory device on the initial rising edge of an external clock signal supplied to the device upon a deselect condition. Upon the first cycle of the select condition, when the external clock signal initially rises, an Output Disable Internal signal remains a high logic state.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

Abstract: A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.

Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode.

Abstract: According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate line of data in the cache memory containing the faulty data. The present invention employs address detection circuitry which detects when a faulty data address stored in the tag RAM is presented during a microprocessor memory cycle and forces the valid bit for that faulty data to a predetermined logic level. When the valid bit associated with the faulty data is set to the predetermined logic level, the tag RAM generates a signal indicative of a "miss" condition. The "miss condition" is communicated to the microprocessor which must access the requested data from main memory, thus effectively bypassing the faulty data. The address detection circuitry of the invalidation circuitry may be expanded to handle any number of faulty data.

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device.